1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Elaboratable
6 from nmigen
.cli
import main
, verilog
8 from ieee754
.fpcommon
.fpbase
import FPNumOut
, FPNumBaseRecord
, FPNumBase
9 from ieee754
.fpcommon
.fpbase
import FPState
10 from .roundz
import FPRoundData
11 from nmutil
.singlepipe
import Object
12 from ieee754
.fpcommon
.getop
import FPPipeContext
17 def __init__(self
, width
, pspec
):
18 self
.z
= Signal(width
, reset_less
=True) # result
19 self
.ctx
= FPPipeContext(width
, pspec
)
21 # this is complicated: it's a workaround, due to the
22 # array-indexing not working properly in nmigen.
23 # self.ports() is used to access the ArrayProxy objects by name,
24 # however it doesn't work recursively. the workaround:
25 # drop the sub-objects into *this* scope and they can be
26 # accessed / set. it's horrible.
27 self
.muxid
= self
.ctx
.muxid
31 return [self
.z
.eq(i
.z
), self
.ctx
.eq(i
.ctx
)]
41 class FPPackMod(Elaboratable
):
43 def __init__(self
, width
, pspec
):
50 return FPRoundData(self
.width
, self
.pspec
)
53 return FPPackData(self
.width
, self
.pspec
)
58 def setup(self
, m
, in_z
):
59 """ links module to inputs and outputs
61 m
.submodules
.pack
= self
62 m
.d
.comb
+= self
.i
.eq(in_z
)
64 def elaborate(self
, platform
):
66 z
= FPNumBaseRecord(self
.width
, False)
67 m
.submodules
.pack_in_z
= in_z
= FPNumBase(self
.i
.z
)
68 #m.submodules.pack_out_z = out_z = FPNumOut(z)
69 m
.d
.comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)
70 with m
.If(~self
.i
.out_do_z
):
71 with m
.If(in_z
.is_overflowed
):
72 m
.d
.comb
+= z
.inf(self
.i
.z
.s
)
74 m
.d
.comb
+= z
.create(self
.i
.z
.s
, self
.i
.z
.e
, self
.i
.z
.m
)
76 m
.d
.comb
+= z
.v
.eq(self
.i
.oz
)
77 m
.d
.comb
+= self
.o
.z
.eq(z
.v
)
81 class FPPack(FPState
):
83 def __init__(self
, width
, id_wid
):
84 FPState
.__init
__(self
, "pack")
85 self
.mod
= FPPackMod(width
)
86 self
.out_z
= self
.ospec()
89 return self
.mod
.ispec()
92 return self
.mod
.ospec()
94 def setup(self
, m
, in_z
):
95 """ links module to inputs and outputs
97 self
.mod
.setup(m
, in_z
)
99 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
100 m
.d
.sync
+= self
.out_z
.ctx
.eq(self
.mod
.o
.ctx
)
103 m
.next
= "pack_put_z"