1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
6 from nmigen
.cli
import main
, verilog
8 from ieee754
.fpcommon
.modbase
import FPModBase
9 from ieee754
.fpcommon
.fpbase
import FPNumBase
, FPNumBaseRecord
10 from ieee754
.fpcommon
.getop
import FPPipeContext
11 from ieee754
.fpcommon
.postnormalise
import FPNorm1Data
16 def __init__(self
, pspec
):
18 self
.z
= FPNumBaseRecord(width
, False, name
="z")
19 self
.ctx
= FPPipeContext(pspec
)
20 self
.muxid
= self
.ctx
.muxid
21 # pipeline bypass [data comes from specialcases]
22 self
.out_do_z
= Signal(reset_less
=True)
23 self
.oz
= Signal(width
, reset_less
=True)
26 ret
= [self
.z
.eq(i
.z
), self
.out_do_z
.eq(i
.out_do_z
), self
.oz
.eq(i
.oz
),
31 class FPRoundMod(FPModBase
):
33 def __init__(self
, pspec
):
34 super().__init
__(pspec
, "roundz")
37 return FPNorm1Data(self
.pspec
)
40 return FPRoundData(self
.pspec
)
42 def elaborate(self
, platform
):
46 comb
+= self
.o
.eq(self
.i
) # copies muxid, z, out_do_z
47 with m
.If(~self
.i
.out_do_z
): # bypass wasn't enabled
48 with m
.If(self
.i
.roundz
):
49 comb
+= self
.o
.z
.m
.eq(self
.i
.z
.m
+ 1) # mantissa up
50 with m
.If(self
.i
.z
.m
== self
.i
.z
.m1s
): # all 1s
52 comb
+= self
.o
.z
.e
.eq(self
.i
.z
.e
+ 1)