src/ieee754/fpdiv/div0.py

   1 """IEEE754 Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Cat, Elaboratable
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
  10 from ieee754.fpcommon.fpbase import FPState
  11 from ieee754.fpcommon.denorm import FPSCData
  12 from ieee754.fpcommon.getop import FPPipeContext
  13 from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInputData
  14
  15
  16 # TODO: delete (replace by DivPipeCoreInputData)
  17 class FPDivStage0Data:
  18
  19     def __init__(self, pspec):
  20         self.z = FPNumBaseRecord(pspec.width, False)
  21         self.out_do_z = Signal(reset_less=True)
  22         self.oz = Signal(pspec.width, reset_less=True)
  23
  24         self.ctx = FPPipeContext(pspec.width, pspec) # context: muxid, operator etc.
  25         self.muxid = self.ctx.muxid             # annoying. complicated.
  26
  27         # TODO: here is where Q and R would be put, and passed
  28         # down to Stage1 processing.
  29
  30         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
  31         self.product = Signal(mw, reset_less=True)
  32
  33     def eq(self, i):
  34         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  35                 self.product.eq(i.product), self.ctx.eq(i.ctx)]
  36
  37
  38 class FPDivStage0Mod(Elaboratable):
  39
  40     def __init__(self, pspec):
  41         self.pspec = pspec
  42         self.i = self.ispec()
  43         self.o = self.ospec()
  44
  45     def ispec(self):
  46         return FPSCData(self.pspec, False)
  47
  48     def ospec(self):
  49         return DivPipeInputData(self.pspec)
  50
  51     def process(self, i):
  52         return self.o
  53
  54     def setup(self, m, i):
  55         """ links module to inputs and outputs
  56         """
  57         m.submodules.div0 = self
  58         m.d.comb += self.i.eq(i)
  59
  60     def elaborate(self, platform):
  61         m = Module()
  62
  63         # XXX TODO, actual DIV code here.  this class would be
  64         # "step one" which takes the pre-normalised data (see ispec) and
  65         # *begins* the processing phase (enters the massive DIV
  66         # pipeline chain) - see ospec.
  67
  68         # INPUT SPEC: FPSCData
  69         # OUTPUT SPEC: DivPipeCoreInputData
  70
  71         # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
  72         # it is PURELY the *ENTRY* point into the chain, performing
  73         # "preparation" work.
  74
  75         with m.If(~self.i.out_do_z):
  76             # do conversion here, of both self.i.a and self.i.b,
  77             # into DivPipeCoreInputData dividend and divisor.
  78
  79             # the mantissas, having been de-normalised (and containing
  80             # a "1" in the MSB) represent numbers in the range 0.5 to
  81             # 0.9999999-recurring.  the min and max range of the
  82             # result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
  83             # (0.99999/0.5).
  84
  85             # zero-extend the mantissas (room for sticky/guard)
  86             # plus the extra MSB.  See DivPipeBaseStage.get_core_config
  87             am0 = Signal(len(self.i.a.m)+3, reset_less=True)
  88             bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
  89             m.d.comb += [
  90                          am0.eq(Cat(0, 0, self.i.a.m, 0)),
  91                          bm0.eq(Cat(0, 0, self.i.b.m, 0))
  92                         ]
  93
  94             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
  95                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
  96                          self.o.dividend.eq(am0), # TODO: check
  97                          self.o.divisor_radicand.eq(bm0), # TODO: check
  98                          self.o.operation.eq(Const(0)) # TODO check: DIV
  99                 ]
 100
 101         # these are required and must not be touched
 102         m.d.comb += self.o.oz.eq(self.i.oz)
 103         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 104         m.d.comb += self.o.ctx.eq(self.i.ctx)
 105
 106         return m
 107
 108
 109 class FPDivStage0(FPState):
 110     """ First stage of div.
 111     """
 112
 113     def __init__(self, pspec):
 114         FPState.__init__(self, "divider_0")
 115         self.mod = FPDivStage0Mod(pspec)
 116         self.o = self.mod.ospec()
 117
 118     def setup(self, m, i):
 119         """ links module to inputs and outputs
 120         """
 121         self.mod.setup(m, i)
 122
 123         # NOTE: these could be done as combinatorial (merge div0+div1)
 124         m.d.sync += self.o.eq(self.mod.o)
 125
 126     def action(self, m):
 127         m.next = "divider_1"