1 """IEEE754 Floating Point Divider
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
6 from nmigen
import Module
, Signal
, Cat
, Elaboratable
7 from nmigen
.cli
import main
, verilog
9 from ieee754
.fpcommon
.fpbase
import (FPNumBaseRecord
, Overflow
)
10 from ieee754
.fpcommon
.fpbase
import FPState
11 from ieee754
.fpcommon
.denorm
import FPSCData
12 from ieee754
.fpcommon
.getop
import FPPipeContext
15 # TODO: delete (replace by DivPipeCoreInputData)
16 class FPDivStage0Data
:
18 def __init__(self
, pspec
):
19 self
.z
= FPNumBaseRecord(pspec
.width
, False)
20 self
.out_do_z
= Signal(reset_less
=True)
21 self
.oz
= Signal(pspec
.width
, reset_less
=True)
23 self
.ctx
= FPPipeContext(pspec
.width
, pspec
) # context: muxid, operator etc.
24 self
.muxid
= self
.ctx
.muxid
# annoying. complicated.
26 # TODO: here is where Q and R would be put, and passed
27 # down to Stage1 processing.
29 mw
= (self
.z
.m_width
)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
30 self
.product
= Signal(mw
, reset_less
=True)
33 return [self
.z
.eq(i
.z
), self
.out_do_z
.eq(i
.out_do_z
), self
.oz
.eq(i
.oz
),
34 self
.product
.eq(i
.product
), self
.ctx
.eq(i
.ctx
)]
37 class FPDivStage0Mod(Elaboratable
):
39 def __init__(self
, pspec
):
45 return FPSCData(self
.pspec
, False)
48 # XXX TODO: replace with DivPipeCoreInputData, here
49 return FPDivStage0Data(self
.pspec
)
54 def setup(self
, m
, i
):
55 """ links module to inputs and outputs
57 m
.submodules
.div0
= self
58 m
.d
.comb
+= self
.i
.eq(i
)
60 def elaborate(self
, platform
):
63 # XXX TODO, actual DIV code here. this class would be
64 # "step one" which takes the pre-normalised data (see ispec) and
65 # *begins* the processing phase (enters the massive DIV
66 # pipeline chain) - see ospec.
68 # INPUT SPEC: FPSCData
69 # OUTPUT SPEC: DivPipeCoreInputData
71 # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
72 # it is PURELY the *ENTRY* point into the chain, performing
76 # store intermediate tests (and zero-extended mantissas)
77 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
78 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
80 am0
.eq(Cat(self
.i
.a
.m
, 0)),
81 bm0
.eq(Cat(self
.i
.b
.m
, 0))
84 with m
.If(~self
.i
.out_do_z
):
85 # do conversion here, of both self.i.a and self.i.b,
86 # into DivPipeCoreInputData dividend and divisor.
88 m
.d
.comb
+= [self
.o
.z
.e
.eq(self
.i
.a
.e
+ self
.i
.b
.e
+ 1),
89 # TODO: no, not product, first stage Q and R etc. etc.
91 self
.o
.product
.eq(am0
* bm0
* 4),
92 self
.o
.z
.s
.eq(self
.i
.a
.s ^ self
.i
.b
.s
)
95 # these are required and must not be touched
96 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
97 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
98 m
.d
.comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)
103 class FPDivStage0(FPState
):
104 """ First stage of div.
107 def __init__(self
, pspec
):
108 FPState
.__init
__(self
, "divider_0")
109 self
.mod
= FPDivStage0Mod(pspec
)
110 self
.o
= self
.mod
.ospec()
112 def setup(self
, m
, i
):
113 """ links module to inputs and outputs
117 # NOTE: these could be done as combinatorial (merge div0+div1)
118 m
.d
.sync
+= self
.o
.eq(self
.mod
.o
)