1 """IEEE754 Floating Point Divider
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
6 from nmigen
import Module
, Signal
, Cat
, Elaboratable
7 from nmigen
.cli
import main
, verilog
9 from ieee754
.fpcommon
.fpbase
import FPNumBaseRecord
10 from ieee754
.fpcommon
.fpbase
import FPState
11 from ieee754
.fpcommon
.denorm
import FPSCData
12 from .div0
import FPDivStage0Data
# TODO: replace with DivPipeCoreInterstageData
15 class FPDivStage1Mod(Elaboratable
):
17 def __init__(self
, pspec
):
23 # TODO: DivPipeCoreInterstageData, here
24 return FPDivStage0Data(self
.pspec
) # Q/Rem (etc) in...
27 # TODO: DivPipeCoreInterstageData, here
28 return FPDivStage0Data(self
.pspec
) # ... Q/Rem (etc) out
33 def setup(self
, m
, i
):
34 """ links module to inputs and outputs
36 m
.submodules
.div0
= self
37 m
.d
.comb
+= self
.i
.eq(i
)
39 def elaborate(self
, platform
):
42 # XXX TODO, actual DIV code here. this class would be
43 # here is where Q and R are used, TODO: Q/REM (etc) need to be in
46 # NOTE: this does ONE step of Q/REM processing. it does NOT do
47 # MULTIPLE stages of Q/REM processing. it *MUST* be PURE
48 # combinatorial and one step ONLY.
50 # store intermediate tests (and zero-extended mantissas)
51 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
52 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
54 am0
.eq(Cat(self
.i
.a
.m
, 0)),
55 bm0
.eq(Cat(self
.i
.b
.m
, 0))
57 # same-sign (both negative or both positive) div mantissas
58 with m
.If(~self
.i
.out_do_z
):
59 m
.d
.comb
+= [self
.o
.z
.e
.eq(self
.i
.a
.e
+ self
.i
.b
.e
+ 1),
60 # TODO: no, not product, first stage Q and R etc. etc.
62 self
.o
.product
.eq(am0
* bm0
* 4),
63 self
.o
.z
.s
.eq(self
.i
.a
.s ^ self
.i
.b
.s
)
66 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
67 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
68 m
.d
.comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)