1 """IEEE754 Floating Point Divider Pipeline
3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4 Copyright (C) 2019 Jacob Lifshay
7 * http://bugs.libre-riscv.org/show_bug.cgi?id=99
8 * http://bugs.libre-riscv.org/show_bug.cgi?id=43
9 * http://bugs.libre-riscv.org/show_bug.cgi?id=44
11 Stack looks like this:
13 scnorm - FPDIVSpecialCasesDeNorm ispec FPBaseData
16 StageChain: FPDIVSpecialCasesMod,
19 pipediv0 - FPDivStagesSetup ispec FPSCData
20 -------- ospec DivPipeInterstageData
22 StageChain: FPDivStage0Mod,
24 DivPipeCalculateStage,
28 pipediv1 - FPDivStagesIntermediate ispec DivPipeInterstageData
29 -------- ospec DivPipeInterstageData
31 StageChain: DivPipeCalculateStage,
37 pipediv5 - FPDivStageFinal ispec FPDivStage0Data
38 -------- ospec FPPostCalcData
40 StageChain: DivPipeCalculateStage,
42 DivPipeCalculateStage,
46 normpack - FPNormToPack ispec FPPostCalcData
47 -------- ospec FPPackData
49 StageChain: Norm1ModSingle,
54 the number of combinatorial StageChains (n_comb_stages) in
55 FPDivStages is an argument arranged to get the length of the whole
56 pipeline down to sane numbers. it specifies the number of "blocks"
57 that will be combinatorially chained together.
59 the reason for keeping the number of stages down is that for every
60 pipeline clock delay, a corresponding ReservationStation is needed.
61 if there are 24 pipeline stages, we need a whopping TWENTY FOUR
62 RS's. that's far too many. 6 is just about an acceptable number.
63 even 8 is starting to get alarmingly high.
66 from nmutil
.singlepipe
import ControlBase
67 from nmutil
.concurrentunit
import ReservationStations
, num_bits
69 from ieee754
.fpcommon
.fpbase
import FPFormat
70 from ieee754
.fpcommon
.normtopack
import FPNormToPack
71 from ieee754
.fpdiv
.specialcases
import FPDIVSpecialCasesDeNorm
72 from ieee754
.fpdiv
.divstages
import (FPDivStagesSetup
,
73 FPDivStagesIntermediate
,
75 from ieee754
.pipeline
import PipelineSpec
76 from ieee754
.div_rem_sqrt_rsqrt
.core
import DivPipeCoreConfig
79 class FPDIVBasePipe(ControlBase
):
80 def __init__(self
, pspec
):
82 ControlBase
.__init
__(self
)
85 # to which the answer: "as few as possible"
86 # is required. too many ReservationStations
87 # means "big problems".
89 # get number of stages, set up loop.
90 n_stages
= pspec
.core_config
.n_stages
91 max_n_comb_stages
= self
.pspec
.n_comb_stages
92 print("n_stages", n_stages
)
98 n_comb_stages
= max_n_comb_stages
99 # needs to convert input from pipestart ospec
102 kls
= FPDivStagesSetup
# does n_comb_stages-1 calcs as well
104 # needs to convert output to pipeend ispec
105 elif stage_idx
+ n_comb_stages
>= n_stages
:
106 kls
= FPDivStagesFinal
# does n_comb_stages-1 calcs as well
108 n_comb_stages
= n_stages
- stage_idx
112 kls
= FPDivStagesIntermediate
# does n_comb_stages calcs
114 # create (in each pipe) a StageChain n_comb_stages in length
115 pipechain
.append(kls(self
.pspec
, n_comb_stages
, stage_idx
))
116 stage_idx
+= n_comb_stages
# increment so that each CalcStage
117 # gets a (correct) unique index
119 self
.pipechain
= pipechain
121 # start and end: unpack/specialcases then normalisation/packing
122 self
.pipestart
= pipestart
= FPDIVSpecialCasesDeNorm(self
.pspec
)
123 self
.pipeend
= pipeend
= FPNormToPack(self
.pspec
)
125 self
._eqs
= self
.connect([pipestart
] + pipechain
+ [pipeend
])
127 def elaborate(self
, platform
):
128 m
= ControlBase
.elaborate(self
, platform
)
131 m
.submodules
.scnorm
= self
.pipestart
132 for i
, p
in enumerate(self
.pipechain
):
133 setattr(m
.submodules
, "pipediv%d" % i
, p
)
134 m
.submodules
.normpack
= self
.pipeend
136 # ControlBase.connect creates the "eqs" needed to connect each pipe
137 m
.d
.comb
+= self
._eqs
143 return x
if x
% mod
== 0 else x
+ mod
- x
% mod
146 class FPDIVMuxInOut(ReservationStations
):
147 """ Reservation-Station version of FPDIV pipeline.
149 * fan-in on inputs (an array of FPBaseData: a,b,mid)
150 * N-stage divider pipeline
151 * fan-out on outputs (an array of FPPackData: z,mid)
153 Fan-in and Fan-out are combinatorial.
155 :op_wid: - set this to the width of an operator which can
156 then be used to change the behaviour of the pipeline.
159 def __init__(self
, width
, num_rows
, op_wid
=2):
160 self
.id_wid
= num_bits(num_rows
)
161 self
.pspec
= PipelineSpec(width
, self
.id_wid
, op_wid
)
163 # get the standard mantissa width, store in the pspec
164 fmt
= FPFormat
.standard(width
)
165 log2_radix
= 3 # tested options so far: 1, 2 and 3.
166 n_comb_stages
= 2 # 2 compute stages per pipeline stage
168 # extra bits needed: guard + round (sticky comes from remainer.bool())
169 fraction_width
= fmt
.fraction_width
172 # rounding width to a multiple of log2_radix is not needed,
173 # DivPipeCoreCalculateStage just internally reduces log2_radix on
175 cfg
= DivPipeCoreConfig(fmt
.width
, fraction_width
, log2_radix
)
177 self
.pspec
.fpformat
= fmt
178 self
.pspec
.n_comb_stages
= n_comb_stages
179 self
.pspec
.core_config
= cfg
181 # XXX TODO - a class (or function?) that takes the pspec (right here)
182 # and creates... "something". that "something" MUST have an eq function
183 # new_pspec = deepcopy(self.pspec)
184 # new_pspec.opkls = DivPipeCoreOperation
185 # self.alu = FPDIVBasePipe(new_pspec)
186 self
.alu
= FPDIVBasePipe(self
.pspec
)
187 ReservationStations
.__init
__(self
, num_rows
)