1 """IEEE Floating Point Divider Pipeline
3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
7 scnorm - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
10 StageChain: FPDIVSpecialCasesMod,
13 pipediv0 - FPDivStagesSetup ispec FPSCData
14 -------- ospec DivPipeCoreInterstageData
16 StageChain: FPDivStage0Mod,
18 DivPipeCalculateStage,
22 pipediv1 - FPDivStagesIntermediate ispec DivPipeCoreInterstageData
23 -------- ospec DivPipeCoreInterstageData
25 StageChain: DivPipeCalculateStage,
31 pipediv5 - FPDivStageFinal ispec FPDivStage0Data
32 -------- ospec FPAddStage1Data
34 StageChain: DivPipeCalculateStage,
36 DivPipeCalculateStage,
40 normpack - FPNormToPack ispec FPAddStage1Data
41 -------- ospec FPPackData
43 StageChain: Norm1ModSingle,
48 the number of combinatorial StageChains (n_comb_stages) in
49 FPDivStages is an argument arranged to get the length of the whole
50 pipeline down to sane numbers.
52 the reason for keeping the number of stages down is that for every
53 pipeline clock delay, a corresponding ReservationStation is needed.
54 if there are 24 pipeline stages, we need a whopping TWENTY FOUR
55 RS's. that's far too many. 6 is just about an acceptable number.
56 even 8 is starting to get alarmingly high.
59 from nmigen
import Module
60 from nmigen
.cli
import main
, verilog
62 from nmutil
.singlepipe
import ControlBase
63 from nmutil
.concurrentunit
import ReservationStations
, num_bits
65 from ieee754
.fpcommon
.getop
import FPADDBaseData
66 from ieee754
.fpcommon
.denorm
import FPSCData
67 from ieee754
.fpcommon
.fpbase
import FPFormat
68 from ieee754
.fpcommon
.pack
import FPPackData
69 from ieee754
.fpcommon
.normtopack
import FPNormToPack
70 from ieee754
.fpdiv
.specialcases
import FPDIVSpecialCasesDeNorm
71 from ieee754
.fpdiv
.divstages
import (FPDivStagesSetup
,
72 FPDivStagesIntermediate
,
74 from ieee754
.pipeline
import PipelineSpec
77 class FPDIVBasePipe(ControlBase
):
78 def __init__(self
, pspec
):
80 ControlBase
.__init
__(self
)
83 n_stages
= 6 # TODO (depends on width)
84 n_comb_stages
= 3 # TODO (depends on how many RS's we want)
86 # to which the answer: "as few as possible"
87 # is required. too many ReservationStations
88 # means "big problems".
90 for i
in range(n_stages
):
92 # needs to convert input from pipestart ospec
94 kls
= FPDivStagesSetup
95 n_comb_stages
-= 1 # reduce due to work done at start
97 # needs to convert output to pipeend ispec
98 elif i
== n_stages
- 1:
99 kls
= FPDivStagesFinal
100 n_comb_stages
-= 1 # FIXME - reduce due to work done at end?
104 kls
= FPDivStagesIntermediate
106 pipechain
.append(kls(self
.pspec
, n_comb_stages
, stage_idx
))
107 stage_idx
+= n_comb_stages
# increment so that each CalcStage
108 # gets a (correct) unique index
110 self
.pipechain
= pipechain
112 # start and end: unpack/specialcases then normalisation/packing
113 self
.pipestart
= FPDIVSpecialCasesDeNorm(self
.pspec
)
114 self
.pipeend
= FPNormToPack(self
.pspec
)
116 self
._eqs
= self
.connect([pipestart
] + pipechain
+ [pipeend
])
118 def elaborate(self
, platform
):
119 m
= ControlBase
.elaborate(self
, platform
)
122 m
.submodules
.scnorm
= self
.pipestart
123 for i
, p
in enumerate(self
.pipechain
):
124 setattr(m
.submodules
, "pipediv%d" % i
, p
)
125 m
.submodules
.normpack
= self
.pipeend
127 # ControlBase.connect creates the "eqs" needed to connect each pipe
128 m
.d
.comb
+= self
._eqs
133 class FPDIVMuxInOut(ReservationStations
):
134 """ Reservation-Station version of FPDIV pipeline.
136 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
137 * N-stage divider pipeline
138 * fan-out on outputs (an array of FPPackData: z,mid)
140 Fan-in and Fan-out are combinatorial.
142 :op_wid: - set this to the width of an operator which can
143 then be used to change the behaviour of the pipeline.
146 def __init__(self
, width
, num_rows
, op_wid
=0):
147 self
.id_wid
= num_bits(width
)
148 self
.pspec
= PipelineSpec(width
, self
.id_wid
, op_wid
)
149 # get the standard mantissa width, store in the pspec
150 # (used in DivPipeBaseStage.get_core_config)
151 p
= FPFormat
.standard(width
)
152 self
.pspec
.m_width
= p
.m_width
154 # XXX TODO - a class (or function?) that takes the pspec (right here)
155 # and creates... "something". that "something" MUST have an eq function
156 # new_pspec = deepcopy(self.pspec)
157 # new_pspec.opkls = DivPipeCoreOperation
158 # self.alu = FPDIVBasePipe(new_pspec)
159 self
.alu
= FPDIVBasePipe(self
.pspec
)
160 ReservationStations
.__init
__(self
, num_rows
)
163 return FPADDBaseData(self
.pspec
)
166 return FPPackData(self
.pspec
)