src/ieee754/fpmul/mul0.py

   1 """IEEE754 Floating Point Multiplier Pipeline
   2
   3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4
   5 """
   6
   7 from nmigen import Module, Signal, Cat, Elaboratable
   8 from nmigen.cli import main, verilog
   9
  10 from ieee754.fpcommon.fpbase import FPNumBaseRecord
  11 from ieee754.fpcommon.denorm import FPSCData
  12 from ieee754.fpcommon.getop import FPPipeContext
  13
  14
  15 class FPMulStage0Data:
  16
  17     def __init__(self, pspec):
  18         width = pspec.width
  19         self.z = FPNumBaseRecord(width, False)
  20         self.out_do_z = Signal(reset_less=True)
  21         self.oz = Signal(width, reset_less=True)
  22         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
  23         self.product = Signal(mw, reset_less=True)
  24         self.ctx = FPPipeContext(pspec)
  25         self.muxid = self.ctx.muxid
  26
  27     def eq(self, i):
  28         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  29                 self.product.eq(i.product), self.ctx.eq(i.ctx)]
  30
  31
  32 class FPMulStage0Mod(Elaboratable):
  33
  34     def __init__(self, pspec):
  35         self.pspec = pspec
  36         self.i = self.ispec()
  37         self.o = self.ospec()
  38
  39     def ispec(self):
  40         return FPSCData(self.pspec, False)
  41
  42     def ospec(self):
  43         return FPMulStage0Data(self.pspec)
  44
  45     def process(self, i):
  46         return self.o
  47
  48     def setup(self, m, i):
  49         """ links module to inputs and outputs
  50         """
  51         m.submodules.mul0 = self
  52         m.d.comb += self.i.eq(i)
  53
  54     def elaborate(self, platform):
  55         m = Module()
  56
  57         # store intermediate tests (and zero-extended mantissas)
  58         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  59         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  60         m.d.comb += [
  61                      am0.eq(Cat(self.i.a.m, 0)),
  62                      bm0.eq(Cat(self.i.b.m, 0))
  63                     ]
  64         # same-sign (both negative or both positive) mul mantissas
  65         with m.If(~self.i.out_do_z):
  66             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  67                          self.o.product.eq(am0 * bm0 * 4),
  68                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  69                 ]
  70
  71         m.d.comb += self.o.oz.eq(self.i.oz)
  72         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  73         m.d.comb += self.o.ctx.eq(self.i.ctx)
  74         return m