1 # IEEE Floating Point Muler (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Elaboratable
6 from nmigen
.cli
import main
, verilog
8 from ieee754
.fpcommon
.fpbase
import FPNumBaseRecord
9 from ieee754
.fpcommon
.fpbase
import FPState
10 from ieee754
.fpcommon
.denorm
import FPSCData
11 from ieee754
.fpcommon
.getop
import FPBaseData
14 class FPMulStage0Data
:
16 def __init__(self
, width
, pspec
):
17 self
.z
= FPNumBaseRecord(width
, False)
18 self
.out_do_z
= Signal(reset_less
=True)
19 self
.oz
= Signal(width
, reset_less
=True)
20 mw
= (self
.z
.m_width
)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
21 self
.product
= Signal(mw
, reset_less
=True)
22 self
.ctx
= FPBaseData(width
, pspec
)
23 self
.mid
= self
.ctx
.mid
26 return [self
.z
.eq(i
.z
), self
.out_do_z
.eq(i
.out_do_z
), self
.oz
.eq(i
.oz
),
27 self
.product
.eq(i
.product
), self
.ctx
.eq(i
.ctx
)]
30 class FPMulStage0Mod(Elaboratable
):
32 def __init__(self
, width
, pspec
):
39 return FPSCData(self
.width
, self
.pspec
, False)
42 return FPMulStage0Data(self
.width
, self
.pspec
)
47 def setup(self
, m
, i
):
48 """ links module to inputs and outputs
50 m
.submodules
.mul0
= self
51 m
.d
.comb
+= self
.i
.eq(i
)
53 def elaborate(self
, platform
):
55 #m.submodules.mul0_in_a = self.i.a
56 #m.submodules.mul0_in_b = self.i.b
57 #m.submodules.mul0_out_z = self.o.z
59 # store intermediate tests (and zero-extended mantissas)
60 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
61 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
63 am0
.eq(Cat(self
.i
.a
.m
, 0)),
64 bm0
.eq(Cat(self
.i
.b
.m
, 0))
66 # same-sign (both negative or both positive) mul mantissas
67 with m
.If(~self
.i
.out_do_z
):
68 m
.d
.comb
+= [self
.o
.z
.e
.eq(self
.i
.a
.e
+ self
.i
.b
.e
+ 1),
69 self
.o
.product
.eq(am0
* bm0
* 4),
70 self
.o
.z
.s
.eq(self
.i
.a
.s ^ self
.i
.b
.s
)
73 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
74 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
75 m
.d
.comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)
79 class FPMulStage0(FPState
):
80 """ First stage of mul.
83 def __init__(self
, width
, id_wid
):
84 FPState
.__init
__(self
, "multiply_0")
85 self
.mod
= FPMulStage0Mod(width
)
86 self
.o
= self
.mod
.ospec()
88 def setup(self
, m
, i
):
89 """ links module to inputs and outputs
93 # NOTE: these could be done as combinatorial (merge mul0+mul1)
94 m
.d
.sync
+= self
.o
.eq(self
.mod
.o
)