1 # IEEE Floating Point Multiplier
3 from nmigen
import Module
, Signal
, Elaboratable
4 from nmigen
.cli
import main
, verilog
6 from ieee754
.fpcommon
.fpbase
import FPState
7 from ieee754
.fpcommon
.postcalc
import FPAddStage1Data
8 from .mul0
import FPMulStage0Data
11 class FPMulStage1Mod(FPState
, Elaboratable
):
12 """ Second stage of mul: preparation for normalisation.
15 def __init__(self
, width
, id_wid
):
22 return FPMulStage0Data(self
.width
, self
.id_wid
)
25 return FPAddStage1Data(self
.width
, self
.id_wid
)
30 def setup(self
, m
, i
):
31 """ links module to inputs and outputs
33 m
.submodules
.mul1
= self
34 m
.submodules
.mul1_out_overflow
= self
.o
.of
36 m
.d
.comb
+= self
.i
.eq(i
)
38 def elaborate(self
, platform
):
40 m
.d
.comb
+= self
.o
.z
.eq(self
.i
.z
)
41 with m
.If(~self
.i
.out_do_z
):
44 self
.o
.z
.m
.eq(self
.i
.product
[mw
+2:]),
45 self
.o
.of
.m0
.eq(self
.i
.product
[mw
+2]),
46 self
.o
.of
.guard
.eq(self
.i
.product
[mw
+1]),
47 self
.o
.of
.round_bit
.eq(self
.i
.product
[mw
]),
48 self
.o
.of
.sticky
.eq(self
.i
.product
[0:mw
].bool())
51 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
52 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
53 m
.d
.comb
+= self
.o
.mid
.eq(self
.i
.mid
)
58 class FPMulStage1(FPState
):
60 def __init__(self
, width
, id_wid
):
61 FPState
.__init
__(self
, "multiply_1")
62 self
.mod
= FPMulStage1Mod(width
)
63 self
.out_z
= FPNumBase(width
, False)
64 self
.out_of
= Overflow()
65 self
.norm_stb
= Signal()
67 def setup(self
, m
, i
):
68 """ links module to inputs and outputs
72 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in mul1 state
74 m
.d
.sync
+= self
.out_of
.eq(self
.mod
.out_of
)
75 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
76 m
.d
.sync
+= self
.norm_stb
.eq(1)
79 m
.next
= "normalise_1"