1 # IEEE Floating Point Multiplier
3 from nmigen
import Module
, Signal
, Elaboratable
4 from nmigen
.cli
import main
, verilog
6 from ieee754
.fpcommon
.fpbase
import FPState
7 from ieee754
.fpcommon
.postcalc
import FPAddStage1Data
8 from .mul0
import FPMulStage0Data
11 class FPMulStage1Mod(FPState
, Elaboratable
):
12 """ Second stage of mul: preparation for normalisation.
13 detects when tot sum is too big (tot[27] is kinda a carry bit)
16 def __init__(self
, width
, id_wid
):
23 return FPMulStage0Data(self
.width
, self
.id_wid
)
26 return FPAddStage1Data(self
.width
, self
.id_wid
)
31 def setup(self
, m
, i
):
32 """ links module to inputs and outputs
34 m
.submodules
.mul1
= self
35 m
.submodules
.mul1_out_overflow
= self
.o
.of
37 m
.d
.comb
+= self
.i
.eq(i
)
39 def elaborate(self
, platform
):
41 m
.d
.comb
+= self
.o
.z
.eq(self
.i
.z
)
42 # tot[-1] (MSB) gets set when the sum overflows. shift result down
43 with m
.If(~self
.i
.out_do_z
):
46 self
.o
.z
.m
.eq(self
.i
.product
[mw
+2:]),
47 self
.o
.of
.m0
.eq(self
.i
.tot
[mw
+2]),
48 self
.o
.of
.guard
.eq(self
.i
.tot
[mw
+1]),
49 self
.o
.of
.round_bit
.eq(self
.i
.tot
[mw
]),
50 self
.o
.of
.sticky
.eq(self
.i
.tot
[0:mw
].bool())
53 m
.d
.comb
+= self
.o
.out_do_z
.eq(self
.i
.out_do_z
)
54 m
.d
.comb
+= self
.o
.oz
.eq(self
.i
.oz
)
55 m
.d
.comb
+= self
.o
.mid
.eq(self
.i
.mid
)
60 class FPMulStage1(FPState
):
62 def __init__(self
, width
, id_wid
):
63 FPState
.__init
__(self
, "multiply_1")
64 self
.mod
= FPMulStage1Mod(width
)
65 self
.out_z
= FPNumBase(width
, False)
66 self
.out_of
= Overflow()
67 self
.norm_stb
= Signal()
69 def setup(self
, m
, i
):
70 """ links module to inputs and outputs
74 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in mul1 state
76 m
.d
.sync
+= self
.out_of
.eq(self
.mod
.out_of
)
77 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
78 m
.d
.sync
+= self
.norm_stb
.eq(1)
81 m
.next
= "normalise_1"