2 from random
import randint
3 from random
import seed
4 from operator
import mul
6 from nmigen
import Module
, Signal
7 from nmigen
.compat
.sim
import run_simulation
9 from ieee754
.fpmul
.fmul
import FPMUL
11 from ieee754
.fpcommon
.test
.unit_test_single
import (get_mantissa
, get_exponent
,
13 is_inf
, is_pos_inf
, is_neg_inf
,
14 match
, get_case
, check_case
, run_fpunit
,
15 run_edge_cases
, run_corner_cases
)
18 def tbench(dut
, maxcount
, num_loops
):
20 yield from check_case(dut
, 0x40000000, 0x40000000, 0x40800000, 0xffcaeefa)
21 yield from check_case(dut
, 0x41400000, 0x40A00000, 0x42700000, 0x3f803262)
27 stimulus_a
= [0xffcaeefa, 0xae430313, 0xa4504d7,
28 0xba57711a, 0xbf9b1e94, 0x34082401, 0x5e8ef81,
30 stimulus_b
= [0x3f803262, 0x901c3214, 0xb4658540,
31 0xee1818c5, 0xc038ed3a, 0xb328cd45, 0x114f3db,
32 0x2f642a39, 0xff3807ab]
33 yield from run_fpunit(dut
, stimulus_a
, stimulus_b
, mul
, get_case
)
34 count
+= len(stimulus_a
)
35 print (count
, "vectors passed")
37 yield from run_corner_cases(dut
, count
, mul
, get_case
)
38 yield from run_edge_cases(dut
, count
, mul
, get_case
, maxcount
, num_loops
)
41 def test1(maxcount
=10, num_loops
=5):
43 run_simulation(dut
, tbench(dut
, maxcount
, num_loops
),
44 vcd_name
="test_mul.vcd")
46 if __name__
== '__main__':
47 test1(maxcount
=1000, num_loops
=1000)