src/ieee754/part/layout_experiment.py

   1 #!/usr/bin/env python3
   2 # SPDX-License-Identifier: LGPL-3-or-later
   3 # See Notices.txt for copyright information
   4 """
   5 Links: https://bugs.libre-soc.org/show_bug.cgi?id=713#c20
   6 """
   7
   8 from nmigen import Signal, Module, Elaboratable, Mux, Cat, Shape, Repl
   9 from nmigen.back.pysim import Simulator, Delay, Settle
  10 from nmigen.cli import rtlil
  11
  12 from collections.abc import Mapping
  13 from pprint import pprint
  14
  15 from ieee754.part_mul_add.partpoints import PartitionPoints
  16
  17
  18 # main fn
  19 def layout(elwid, signed, part_counts, lane_shapes):
  20     # identify if the lane_shapes is a mapping (dict, etc.)
  21     if not isinstance(lane_shapes, Mapping):
  22         lane_shapes = {i: lane_shapes for i in part_counts}
  23     part_wid = -min(-lane_shapes[i] // c for i, c in part_counts.items())
  24     part_count = max(part_counts.values())
  25     width = part_wid * part_count
  26     points = {}
  27     for i, c in part_counts.items():
  28         def add_p(p):
  29             points[p] = points.get(p, False) | (elwid == i)
  30         for start in range(0, part_count, c):
  31             add_p(start * part_wid) # start of lane
  32             add_p(start * part_wid + lane_shapes[i]) # start of padding
  33     points.pop(0, None)
  34     points.pop(width, None)
  35     return (PartitionPoints(points), width, lane_shapes,
  36         part_wid, part_count)
  37
  38 if __name__ == '__main__':
  39     part_counts = {
  40         0: 1,
  41         1: 1,
  42         2: 2,
  43         3: 4,
  44     }
  45
  46     for i in range(4):
  47         pprint((i, layout(i, True, part_counts, 3)))
  48
  49     l = {0: 5, 1: 6, 2: 12, 3: 24}
  50     for i in range(4):
  51         pprint((i, layout(i, False, part_counts, l)))
  52
  53     # https://bugs.libre-soc.org/show_bug.cgi?id=713#c30
  54     elwid = Signal(2)
  55     pp,b,c,d,e = layout(elwid, False, part_counts, l)
  56     pprint ((pp,b,c,d,e))
  57
  58     m = Module()
  59     def process():
  60         for i in range(4):
  61             yield elwid.eq(i)
  62             yield Settle()
  63             ppt = []
  64             for pval in list(pp.values()):
  65                 val = yield pval # get nmigen to evaluate pp
  66                 ppt.append(val)
  67             pprint((i, (ppt,b,c,d,e)))
  68     sim = Simulator(m)
  69     sim.add_process(process)
  70     sim.run()