src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  21 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
  22 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
  23 from ieee754.part_mul_add.partpoints import make_partition
  24 from operator import or_, xor, and_, not_
  25
  26 from nmigen import (Signal, Const)
  27
  28
  29 def getsig(op1):
  30     if isinstance(op1, PartitionedSignal):
  31         op1 = op1.sig
  32     return op1
  33
  34
  35 def applyop(op1, op2, op):
  36     return op(getsig(op1), getsig(op2))
  37
  38
  39 class PartitionedSignal:
  40     def __init__(self, mask, *args, **kwargs):
  41         self.sig = Signal(*args, **kwargs)
  42         width = self.sig.shape()[0]  # get signal width
  43         # create partition points
  44         self.partpoints = make_partition(mask, width)
  45         self.modnames = {}
  46         for name in ['add', 'eq', 'gt', 'ge', 'ls']:
  47             self.modnames[name] = 0
  48
  49     def set_module(self, m):
  50         self.m = m
  51
  52     def get_modname(self, category):
  53         self.modnames[category] += 1
  54         return "%s_%d" % (category, self.modnames[category])
  55
  56     def eq(self, val):
  57         return self.sig.eq(getsig(val))
  58
  59     # unary ops that do not require partitioning
  60
  61     def __invert__(self):
  62         return ~self.sig
  63
  64     # unary ops that require partitioning
  65
  66     def __neg__(self):
  67         z = Const(0, len(self.partpoints)+1)
  68         result, _ = self.add_op(self, ~0, carry=z)  # TODO, subop
  69         return result
  70
  71     # binary ops that don't require partitioning
  72
  73     def __and__(self, other):
  74         return applyop(self, other, and_)
  75
  76     def __rand__(self, other):
  77         return applyop(other, self, and_)
  78
  79     def __or__(self, other):
  80         return applyop(self, other, or_)
  81
  82     def __ror__(self, other):
  83         return applyop(other, self, or_)
  84
  85     def __xor__(self, other):
  86         return applyop(self, other, xor)
  87
  88     def __rxor__(self, other):
  89         return applyop(other, self, xor)
  90
  91     # binary ops that need partitioning
  92
  93     # TODO: detect if the 2nd operand is a Const, a Signal or a
  94     # PartitionedSignal.  if it's a Const or a Signal, a global shift
  95     # can occur.  if it's a PartitionedSignal, that's much more interesting.
  96     def ls_op(self, op1, op2, carry, shr_flag=0):
  97         op1 = getsig(op1)
  98         if isinstance(op2, Const) or isinstance(op2, Signal):
  99             scalar = True
 100             shape = op1.shape()
 101             pa = PartitionedScalarShift(shape[0], self.partpoints)
 102         else:
 103             scalar = False
 104             op2 = getsig(op2)
 105             shape = op1.shape()
 106             pa = PartitionedDynamicShift(shape[0], self.partpoints)
 107         setattr(self.m.submodules, self.get_modname('ls'), pa)
 108         comb = self.m.d.comb
 109         if scalar:
 110             comb += pa.data.eq(op1)
 111             comb += pa.shifter.eq(op2)
 112             comb += pa.shift_right.eq(shr_flag)
 113         else:
 114             comb += pa.a.eq(op1)
 115             comb += pa.b.eq(op2)
 116             comb += pa.shift_right.eq(shr_flag)
 117         # XXX TODO: carry-in, carry-out
 118         #comb += pa.carry_in.eq(carry)
 119         return (pa.output, 0)
 120
 121     def __lshift__(self, other):
 122         z = Const(0, len(self.partpoints)+1)
 123         result, _ = self.ls_op(self, other, carry=z) # TODO, carry
 124         return result
 125
 126     def __rlshift__(self, other):
 127         raise NotImplementedError
 128         return Operator("<<", [other, self])
 129
 130     def __rshift__(self, other):
 131         z = Const(0, len(self.partpoints)+1)
 132         result, _ = self.ls_op(self, other, carry=z, shr_flag=1) # TODO, carry
 133         return result
 134
 135     def __rrshift__(self, other):
 136         raise NotImplementedError
 137         return Operator(">>", [other, self])
 138
 139     def add_op(self, op1, op2, carry):
 140         op1 = getsig(op1)
 141         op2 = getsig(op2)
 142         shape = op1.shape()
 143         pa = PartitionedAdder(shape[0], self.partpoints)
 144         setattr(self.m.submodules, self.get_modname('add'), pa)
 145         comb = self.m.d.comb
 146         comb += pa.a.eq(op1)
 147         comb += pa.b.eq(op2)
 148         comb += pa.carry_in.eq(carry)
 149         return (pa.output, pa.carry_out)
 150
 151     def sub_op(self, op1, op2, carry=~0):
 152         op1 = getsig(op1)
 153         op2 = getsig(op2)
 154         shape = op1.shape()
 155         pa = PartitionedAdder(shape[0], self.partpoints)
 156         setattr(self.m.submodules, self.get_modname('add'), pa)
 157         comb = self.m.d.comb
 158         comb += pa.a.eq(op1)
 159         comb += pa.b.eq(~op2)
 160         comb += pa.carry_in.eq(carry)
 161         return (pa.output, pa.carry_out)
 162
 163     def __add__(self, other):
 164         result, _ = self.add_op(self, other, carry=0)
 165         return result
 166
 167     def __radd__(self, other):
 168         result, _ = self.add_op(other, self)
 169         return result
 170
 171     def __sub__(self, other):
 172         result, _ = self.sub_op(self, other)
 173         return result
 174
 175     def __rsub__(self, other):
 176         result, _ = self.sub_op(other, self)
 177         return result
 178
 179     def __mul__(self, other):
 180         return Operator("*", [self, other])
 181
 182     def __rmul__(self, other):
 183         return Operator("*", [other, self])
 184
 185     def __check_divisor(self):
 186         width, signed = self.shape()
 187         if signed:
 188             # Python's division semantics and Verilog's division semantics
 189             # differ for negative divisors (Python uses div/mod, Verilog
 190             # uses quo/rem); for now, avoid the issue
 191             # completely by prohibiting such division operations.
 192             raise NotImplementedError(
 193                     "Division by a signed value is not supported")
 194
 195     def __mod__(self, other):
 196         raise NotImplementedError
 197         other = Value.cast(other)
 198         other.__check_divisor()
 199         return Operator("%", [self, other])
 200
 201     def __rmod__(self, other):
 202         raise NotImplementedError
 203         self.__check_divisor()
 204         return Operator("%", [other, self])
 205
 206     def __floordiv__(self, other):
 207         raise NotImplementedError
 208         other = Value.cast(other)
 209         other.__check_divisor()
 210         return Operator("//", [self, other])
 211
 212     def __rfloordiv__(self, other):
 213         raise NotImplementedError
 214         self.__check_divisor()
 215         return Operator("//", [other, self])
 216
 217     # binary comparison ops that need partitioning
 218
 219     def _compare(self, width, op1, op2, opname, optype):
 220         # print (opname, op1, op2)
 221         pa = PartitionedEqGtGe(width, self.partpoints)
 222         setattr(self.m.submodules, self.get_modname(opname), pa)
 223         comb = self.m.d.comb
 224         comb += pa.opcode.eq(optype)  # set opcode
 225         if isinstance(op1, PartitionedSignal):
 226             comb += pa.a.eq(op1.sig)
 227         else:
 228             comb += pa.a.eq(op1)
 229         if isinstance(op2, PartitionedSignal):
 230             comb += pa.b.eq(op2.sig)
 231         else:
 232             comb += pa.b.eq(op2)
 233         return pa.output
 234
 235     def __eq__(self, other):
 236         width = self.sig.shape()[0]
 237         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 238
 239     def __ne__(self, other):
 240         width = self.sig.shape()[0]
 241         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 242         ne = Signal(eq.width)
 243         self.m.d.comb += ne.eq(~eq)
 244         return ne
 245
 246     def __gt__(self, other):
 247         width = self.sig.shape()[0]
 248         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 249
 250     def __lt__(self, other):
 251         width = self.sig.shape()[0]
 252         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 253
 254     def __ge__(self, other):
 255         width = self.sig.shape()[0]
 256         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 257
 258     def __le__(self, other):
 259         width = self.sig.shape()[0]
 260         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 261
 262     # useful operators
 263
 264     def bool(self):
 265         """Conversion to boolean.
 266
 267         Returns
 268         -------
 269         Value, out
 270             ``1`` if any bits are set, ``0`` otherwise.
 271         """
 272         raise NotImplementedError
 273         return Operator("b", [self])
 274
 275     def any(self):
 276         """Check if any bits are ``1``.
 277
 278         Returns
 279         -------
 280         Value, out
 281             ``1`` if any bits are set, ``0`` otherwise.
 282         """
 283         raise NotImplementedError
 284         return Operator("r|", [self])
 285
 286     def all(self):
 287         """Check if all bits are ``1``.
 288
 289         Returns
 290         -------
 291         Value, out
 292             ``1`` if all bits are set, ``0`` otherwise.
 293         """
 294         raise NotImplementedError
 295         return Operator("r&", [self])
 296
 297     def xor(self):
 298         """Compute pairwise exclusive-or of every bit.
 299
 300         Returns
 301         -------
 302         Value, out
 303             ``1`` if an odd number of bits are set, ``0`` if an
 304                   even number of bits are set.
 305         """
 306         # XXXX TODO: return partition-mask-sized set of bits
 307         raise NotImplementedError
 308         return Operator("r^", [self])
 309
 310     def implies(premise, conclusion):
 311         """Implication.
 312
 313         Returns
 314         -------
 315         Value, out
 316             ``0`` if ``premise`` is true and ``conclusion`` is not,
 317             ``1`` otherwise.
 318         """
 319         # amazingly, this should actually work.
 320         return ~premise | conclusion