1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 dynamic-partitionable class similar to Signal, which, when the partition
8 is fully open will be identical to Signal. when partitions are closed,
9 the class turns into a SIMD variant of Signal. *this is dynamic*.
11 the basic fundamental idea is: write code once, and if you want a SIMD
12 version of it, use PartitionedSignal in place of Signal. job done.
13 this however requires the code to *not* be designed to use nmigen.If,
14 nmigen.Case, or other constructs: only Mux and other logic.
16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
19 from ieee754
.part_mul_add
.adder
import PartitionedAdder
20 from ieee754
.part_cmp
.eq_gt_ge
import PartitionedEqGtGe
21 from ieee754
.part_shift
.part_shift_dynamic
import PartitionedDynamicShift
22 from ieee754
.part_shift
.part_shift_scalar
import PartitionedScalarShift
23 from ieee754
.part_mul_add
.partpoints
import make_partition
24 from operator
import or_
, xor
, and_
, not_
26 from nmigen
import (Signal
, Const
)
30 if isinstance(op1
, PartitionedSignal
):
35 def applyop(op1
, op2
, op
):
36 return op(getsig(op1
), getsig(op2
))
39 class PartitionedSignal
:
40 def __init__(self
, mask
, *args
, **kwargs
):
41 self
.sig
= Signal(*args
, **kwargs
)
42 width
= self
.sig
.shape()[0] # get signal width
43 # create partition points
44 self
.partpoints
= make_partition(mask
, width
)
46 for name
in ['add', 'eq', 'gt', 'ge', 'ls']:
47 self
.modnames
[name
] = 0
49 def set_module(self
, m
):
52 def get_modname(self
, category
):
53 self
.modnames
[category
] += 1
54 return "%s_%d" % (category
, self
.modnames
[category
])
57 return self
.sig
.eq(getsig(val
))
59 # unary ops that do not require partitioning
64 # unary ops that require partitioning
67 z
= Const(0, len(self
.partpoints
)+1)
68 result
, _
= self
.add_op(self
, ~
0, carry
=z
) # TODO, subop
71 # binary ops that don't require partitioning
73 def __and__(self
, other
):
74 return applyop(self
, other
, and_
)
76 def __rand__(self
, other
):
77 return applyop(other
, self
, and_
)
79 def __or__(self
, other
):
80 return applyop(self
, other
, or_
)
82 def __ror__(self
, other
):
83 return applyop(other
, self
, or_
)
85 def __xor__(self
, other
):
86 return applyop(self
, other
, xor
)
88 def __rxor__(self
, other
):
89 return applyop(other
, self
, xor
)
91 # binary ops that need partitioning
93 # TODO: detect if the 2nd operand is a Const, a Signal or a
94 # PartitionedSignal. if it's a Const or a Signal, a global shift
95 # can occur. if it's a PartitionedSignal, that's much more interesting.
96 def ls_op(self
, op1
, op2
, carry
):
98 if isinstance(op2
, Const
) or isinstance(op2
, Signal
):
101 pa
= PartitionedScalarShift(shape
[0], self
.partpoints
)
106 pa
= PartitionedDynamicShift(shape
[0], self
.partpoints
)
107 setattr(self
.m
.submodules
, self
.get_modname('ls'), pa
)
110 comb
+= pa
.data
.eq(op1
)
111 comb
+= pa
.shifter
.eq(op2
)
115 # XXX TODO: carry-in, carry-out
116 #comb += pa.carry_in.eq(carry)
117 return (pa
.output
, 0)
119 def __lshift__(self
, other
):
120 z
= Const(0, len(self
.partpoints
)+1)
121 result
, _
= self
.ls_op(self
, other
, carry
=z
) # TODO, carry
124 def __rlshift__(self
, other
):
125 raise NotImplementedError
126 return Operator("<<", [other
, self
])
128 def __rshift__(self
, other
):
129 raise NotImplementedError
130 return Operator(">>", [self
, other
])
132 def __rrshift__(self
, other
):
133 raise NotImplementedError
134 return Operator(">>", [other
, self
])
136 def add_op(self
, op1
, op2
, carry
):
140 pa
= PartitionedAdder(shape
[0], self
.partpoints
)
141 setattr(self
.m
.submodules
, self
.get_modname('add'), pa
)
145 comb
+= pa
.carry_in
.eq(carry
)
146 return (pa
.output
, pa
.carry_out
)
148 def sub_op(self
, op1
, op2
, carry
=~
0):
152 pa
= PartitionedAdder(shape
[0], self
.partpoints
)
153 setattr(self
.m
.submodules
, self
.get_modname('add'), pa
)
156 comb
+= pa
.b
.eq(~op2
)
157 comb
+= pa
.carry_in
.eq(carry
)
158 return (pa
.output
, pa
.carry_out
)
160 def __add__(self
, other
):
161 result
, _
= self
.add_op(self
, other
, carry
=0)
164 def __radd__(self
, other
):
165 result
, _
= self
.add_op(other
, self
)
168 def __sub__(self
, other
):
169 result
, _
= self
.sub_op(self
, other
)
172 def __rsub__(self
, other
):
173 result
, _
= self
.sub_op(other
, self
)
176 def __mul__(self
, other
):
177 return Operator("*", [self
, other
])
179 def __rmul__(self
, other
):
180 return Operator("*", [other
, self
])
182 def __check_divisor(self
):
183 width
, signed
= self
.shape()
185 # Python's division semantics and Verilog's division semantics
186 # differ for negative divisors (Python uses div/mod, Verilog
187 # uses quo/rem); for now, avoid the issue
188 # completely by prohibiting such division operations.
189 raise NotImplementedError(
190 "Division by a signed value is not supported")
192 def __mod__(self
, other
):
193 raise NotImplementedError
194 other
= Value
.cast(other
)
195 other
.__check
_divisor
()
196 return Operator("%", [self
, other
])
198 def __rmod__(self
, other
):
199 raise NotImplementedError
200 self
.__check
_divisor
()
201 return Operator("%", [other
, self
])
203 def __floordiv__(self
, other
):
204 raise NotImplementedError
205 other
= Value
.cast(other
)
206 other
.__check
_divisor
()
207 return Operator("//", [self
, other
])
209 def __rfloordiv__(self
, other
):
210 raise NotImplementedError
211 self
.__check
_divisor
()
212 return Operator("//", [other
, self
])
214 # binary comparison ops that need partitioning
216 def _compare(self
, width
, op1
, op2
, opname
, optype
):
217 # print (opname, op1, op2)
218 pa
= PartitionedEqGtGe(width
, self
.partpoints
)
219 setattr(self
.m
.submodules
, self
.get_modname(opname
), pa
)
221 comb
+= pa
.opcode
.eq(optype
) # set opcode
222 if isinstance(op1
, PartitionedSignal
):
223 comb
+= pa
.a
.eq(op1
.sig
)
226 if isinstance(op2
, PartitionedSignal
):
227 comb
+= pa
.b
.eq(op2
.sig
)
232 def __eq__(self
, other
):
233 width
= self
.sig
.shape()[0]
234 return self
._compare
(width
, self
, other
, "eq", PartitionedEqGtGe
.EQ
)
236 def __ne__(self
, other
):
237 width
= self
.sig
.shape()[0]
238 eq
= self
._compare
(width
, self
, other
, "eq", PartitionedEqGtGe
.EQ
)
239 ne
= Signal(eq
.width
)
240 self
.m
.d
.comb
+= ne
.eq(~eq
)
243 def __gt__(self
, other
):
244 width
= self
.sig
.shape()[0]
245 return self
._compare
(width
, self
, other
, "gt", PartitionedEqGtGe
.GT
)
247 def __lt__(self
, other
):
248 width
= self
.sig
.shape()[0]
249 return self
._compare
(width
, other
, self
, "gt", PartitionedEqGtGe
.GT
)
251 def __ge__(self
, other
):
252 width
= self
.sig
.shape()[0]
253 return self
._compare
(width
, self
, other
, "ge", PartitionedEqGtGe
.GE
)
255 def __le__(self
, other
):
256 width
= self
.sig
.shape()[0]
257 return self
._compare
(width
, other
, self
, "ge", PartitionedEqGtGe
.GE
)
262 """Conversion to boolean.
267 ``1`` if any bits are set, ``0`` otherwise.
269 raise NotImplementedError
270 return Operator("b", [self
])
273 """Check if any bits are ``1``.
278 ``1`` if any bits are set, ``0`` otherwise.
280 raise NotImplementedError
281 return Operator("r|", [self
])
284 """Check if all bits are ``1``.
289 ``1`` if all bits are set, ``0`` otherwise.
291 raise NotImplementedError
292 return Operator("r&", [self
])
295 """Compute pairwise exclusive-or of every bit.
300 ``1`` if an odd number of bits are set, ``0`` if an
301 even number of bits are set.
303 # XXXX TODO: return partition-mask-sized set of bits
304 raise NotImplementedError
305 return Operator("r^", [self
])
307 def implies(premise
, conclusion
):
313 ``0`` if ``premise`` is true and ``conclusion`` is not,
316 # amazingly, this should actually work.
317 return ~premise | conclusion