src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use SimdSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  21 from ieee754.part_bits.xor import PartitionedXOR
  22 from ieee754.part_bits.bool import PartitionedBool
  23 from ieee754.part_bits.all import PartitionedAll
  24 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
  25 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
  26 from ieee754.part_mul_add.partpoints import make_partition2, PartitionPoints
  27 from ieee754.part_mux.part_mux import PMux
  28 from ieee754.part_ass.passign import PAssign
  29 from ieee754.part_cat.pcat import PCat
  30 from ieee754.part_repl.prepl import PRepl
  31 from operator import or_, xor, and_, not_
  32
  33 from nmigen import (Signal, Const, Cat)
  34 from nmigen.hdl.ast import UserValue, Shape
  35
  36
  37 def getsig(op1):
  38     if isinstance(op1, SimdSignal):
  39         op1 = op1.sig
  40     return op1
  41
  42
  43 def applyop(op1, op2, op):
  44     if isinstance(op1, SimdSignal):
  45         result = SimdSignal.like(op1)
  46     else:
  47         result = SimdSignal.like(op2)
  48     result.m.d.comb += result.sig.eq(op(getsig(op1), getsig(op2)))
  49     return result
  50
  51
  52 global modnames
  53 modnames = {}
  54 # for sub-modules to be created on-demand. Mux is done slightly
  55 # differently (has its own global)
  56 for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor', 'bool', 'all']:
  57     modnames[name] = 0
  58
  59
  60 # Prototype https://bugs.libre-soc.org/show_bug.cgi?id=713#c53
  61 # this provides a "compatibility" layer with existing SimdSignal
  62 # behaviour.  the idea is that this interface defines which "combinations"
  63 # of partition selections are relevant, and as an added bonus it says
  64 # which partition lanes are completely irrelevant (padding, blank).
  65 class PartType:  # TODO decide name
  66     def __init__(self, psig):
  67         self.psig = psig
  68
  69     def get_mask(self):
  70         return list(self.psig.partpoints.values())
  71
  72     def get_switch(self):
  73         return Cat(self.get_mask())
  74
  75     def get_cases(self):
  76         return range(1 << len(self.get_mask()))
  77
  78     @property
  79     def blanklanes(self):
  80         return 0
  81
  82 # this one would be an elwidth version
  83 # see https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
  84 # it requires an "adapter" which is the layout() function
  85 # where the PartitionPoints was *created* by the layout()
  86 # function and this class then "understands" the relationship
  87 # between elwidth and the PartitionPoints that were created
  88 # by layout()
  89
  90
  91 class ElWidthPartType:  # TODO decide name
  92     def __init__(self, psig):
  93         self.psig = psig
  94
  95     def get_mask(self):
  96         ppoints, pbits = layout()
  97         return ppoints.values()  # i think
  98
  99     def get_switch(self):
 100         return self.psig.elwidth
 101
 102     def get_cases(self):
 103         ppoints, pbits = layout()
 104         return pbits
 105
 106     @property
 107     def blanklanes(self):
 108         return 0  # TODO
 109
 110
 111 class SimdSignal(UserValue):
 112     # XXX ################################################### XXX
 113     # XXX Keep these functions in the same order as ast.Value XXX
 114     # XXX ################################################### XXX
 115     def __init__(self, mask, *args, src_loc_at=0, **kwargs):
 116         super().__init__(src_loc_at=src_loc_at)
 117         self.sig = Signal(*args, **kwargs)
 118         width = len(self.sig)  # get signal width
 119         # create partition points
 120         if isinstance(mask, PartitionPoints):
 121             self.partpoints = mask
 122         else:
 123             self.partpoints = make_partition2(mask, width)
 124         self.ptype = PartType(self)
 125
 126     def set_module(self, m):
 127         self.m = m
 128
 129     def get_modname(self, category):
 130         modnames[category] += 1
 131         return "%s_%d" % (category, modnames[category])
 132
 133     @staticmethod
 134     def like(other, *args, **kwargs):
 135         """Builds a new SimdSignal with the same PartitionPoints and
 136         Signal properties as the other"""
 137         result = SimdSignal(PartitionPoints(other.partpoints))
 138         result.sig = Signal.like(other.sig, *args, **kwargs)
 139         result.m = other.m
 140         return result
 141
 142     def lower(self):
 143         return self.sig
 144
 145     # nmigen-redirected constructs (Mux, Cat, Switch, Assign)
 146
 147     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=458
 148     # def __Part__(self, offset, width, stride=1, *, src_loc_at=0):
 149
 150     def __Repl__(self, count, *, src_loc_at=0):
 151         return PRepl(self.m, self, count, self.ptype)
 152
 153     def __Cat__(self, *args, src_loc_at=0):
 154         args = [self] + list(args)
 155         for sig in args:
 156             assert isinstance(sig, SimdSignal), \
 157                 "All SimdSignal.__Cat__ arguments must be " \
 158                 "a SimdSignal. %s is not." % repr(sig)
 159         return PCat(self.m, args, self.ptype)
 160
 161     def __Mux__(self, val1, val2):
 162         # print ("partsig mux", self, val1, val2)
 163         assert len(val1) == len(val2), \
 164             "SimdSignal width sources must be the same " \
 165             "val1 == %d, val2 == %d" % (len(val1), len(val2))
 166         return PMux(self.m, self.partpoints, self, val1, val2, self.ptype)
 167
 168     def __Assign__(self, val, *, src_loc_at=0):
 169         # print ("partsig ass", self, val)
 170         return PAssign(self.m, self, val, self.ptype)
 171
 172     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=458
 173     # def __Switch__(self, cases, *, src_loc=None, src_loc_at=0,
 174     #                               case_src_locs={}):
 175
 176     # no override needed, Value.__bool__ sufficient
 177     # def __bool__(self):
 178
 179     # unary ops that do not require partitioning
 180
 181     def __invert__(self):
 182         result = SimdSignal.like(self)
 183         self.m.d.comb += result.sig.eq(~self.sig)
 184         return result
 185
 186     # unary ops that require partitioning
 187
 188     def __neg__(self):
 189         z = Const(0, len(self.sig))
 190         result, _ = self.sub_op(z, self)
 191         return result
 192
 193     # binary ops that need partitioning
 194
 195     def add_op(self, op1, op2, carry):
 196         op1 = getsig(op1)
 197         op2 = getsig(op2)
 198         pa = PartitionedAdder(len(op1), self.partpoints)
 199         setattr(self.m.submodules, self.get_modname('add'), pa)
 200         comb = self.m.d.comb
 201         comb += pa.a.eq(op1)
 202         comb += pa.b.eq(op2)
 203         comb += pa.carry_in.eq(carry)
 204         result = SimdSignal.like(self)
 205         comb += result.sig.eq(pa.output)
 206         return result, pa.carry_out
 207
 208     def sub_op(self, op1, op2, carry=~0):
 209         op1 = getsig(op1)
 210         op2 = getsig(op2)
 211         pa = PartitionedAdder(len(op1), self.partpoints)
 212         setattr(self.m.submodules, self.get_modname('add'), pa)
 213         comb = self.m.d.comb
 214         comb += pa.a.eq(op1)
 215         comb += pa.b.eq(~op2)
 216         comb += pa.carry_in.eq(carry)
 217         result = SimdSignal.like(self)
 218         comb += result.sig.eq(pa.output)
 219         return result, pa.carry_out
 220
 221     def __add__(self, other):
 222         result, _ = self.add_op(self, other, carry=0)
 223         return result
 224
 225     def __radd__(self, other):
 226         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 227         result, _ = self.add_op(other, self)
 228         return result
 229
 230     def __sub__(self, other):
 231         result, _ = self.sub_op(self, other)
 232         return result
 233
 234     def __rsub__(self, other):
 235         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 236         result, _ = self.sub_op(other, self)
 237         return result
 238
 239     def __mul__(self, other):
 240         raise NotImplementedError  # too complicated at the moment
 241         return Operator("*", [self, other])
 242
 243     def __rmul__(self, other):
 244         raise NotImplementedError  # too complicated at the moment
 245         return Operator("*", [other, self])
 246
 247     # not needed: same as Value.__check_divisor
 248     # def __check_divisor(self):
 249
 250     def __mod__(self, other):
 251         raise NotImplementedError
 252         other = Value.cast(other)
 253         other.__check_divisor()
 254         return Operator("%", [self, other])
 255
 256     def __rmod__(self, other):
 257         raise NotImplementedError
 258         self.__check_divisor()
 259         return Operator("%", [other, self])
 260
 261     def __floordiv__(self, other):
 262         raise NotImplementedError
 263         other = Value.cast(other)
 264         other.__check_divisor()
 265         return Operator("//", [self, other])
 266
 267     def __rfloordiv__(self, other):
 268         raise NotImplementedError
 269         self.__check_divisor()
 270         return Operator("//", [other, self])
 271
 272     # not needed: same as Value.__check_shamt
 273     # def __check_shamt(self):
 274
 275     # TODO: detect if the 2nd operand is a Const, a Signal or a
 276     # SimdSignal.  if it's a Const or a Signal, a global shift
 277     # can occur.  if it's a SimdSignal, that's much more interesting.
 278     def ls_op(self, op1, op2, carry, shr_flag=0):
 279         op1 = getsig(op1)
 280         if isinstance(op2, Const) or isinstance(op2, Signal):
 281             scalar = True
 282             pa = PartitionedScalarShift(len(op1), self.partpoints)
 283         else:
 284             scalar = False
 285             op2 = getsig(op2)
 286             pa = PartitionedDynamicShift(len(op1), self.partpoints)
 287         # else:
 288         #   TODO: case where the *shifter* is a SimdSignal but
 289         #   the thing *being* Shifted is a scalar (Signal, expression)
 290         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 291         setattr(self.m.submodules, self.get_modname('ls'), pa)
 292         comb = self.m.d.comb
 293         if scalar:
 294             comb += pa.data.eq(op1)
 295             comb += pa.shifter.eq(op2)
 296             comb += pa.shift_right.eq(shr_flag)
 297         else:
 298             comb += pa.a.eq(op1)
 299             comb += pa.b.eq(op2)
 300             comb += pa.shift_right.eq(shr_flag)
 301         # XXX TODO: carry-in, carry-out (for arithmetic shift)
 302         #comb += pa.carry_in.eq(carry)
 303         return (pa.output, 0)
 304
 305     def __lshift__(self, other):
 306         z = Const(0, len(self.partpoints)+1)
 307         result, _ = self.ls_op(self, other, carry=z)  # TODO, carry
 308         return result
 309
 310     def __rlshift__(self, other):
 311         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 312         raise NotImplementedError
 313         return Operator("<<", [other, self])
 314
 315     def __rshift__(self, other):
 316         z = Const(0, len(self.partpoints)+1)
 317         result, _ = self.ls_op(self, other, carry=z, shr_flag=1)  # TODO, carry
 318         return result
 319
 320     def __rrshift__(self, other):
 321         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 322         raise NotImplementedError
 323         return Operator(">>", [other, self])
 324
 325     # binary ops that don't require partitioning
 326
 327     def __and__(self, other):
 328         return applyop(self, other, and_)
 329
 330     def __rand__(self, other):
 331         return applyop(other, self, and_)
 332
 333     def __or__(self, other):
 334         return applyop(self, other, or_)
 335
 336     def __ror__(self, other):
 337         return applyop(other, self, or_)
 338
 339     def __xor__(self, other):
 340         return applyop(self, other, xor)
 341
 342     def __rxor__(self, other):
 343         return applyop(other, self, xor)
 344
 345     # binary comparison ops that need partitioning
 346
 347     def _compare(self, width, op1, op2, opname, optype):
 348         # print (opname, op1, op2)
 349         pa = PartitionedEqGtGe(width, self.partpoints)
 350         setattr(self.m.submodules, self.get_modname(opname), pa)
 351         comb = self.m.d.comb
 352         comb += pa.opcode.eq(optype)  # set opcode
 353         if isinstance(op1, SimdSignal):
 354             comb += pa.a.eq(op1.sig)
 355         else:
 356             comb += pa.a.eq(op1)
 357         if isinstance(op2, SimdSignal):
 358             comb += pa.b.eq(op2.sig)
 359         else:
 360             comb += pa.b.eq(op2)
 361         return pa.output
 362
 363     def __eq__(self, other):
 364         width = len(self.sig)
 365         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 366
 367     def __ne__(self, other):
 368         width = len(self.sig)
 369         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 370         ne = Signal(eq.width)
 371         self.m.d.comb += ne.eq(~eq)
 372         return ne
 373
 374     def __lt__(self, other):
 375         width = len(self.sig)
 376         # swap operands, use gt to do lt
 377         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 378
 379     def __le__(self, other):
 380         width = len(self.sig)
 381         # swap operands, use ge to do le
 382         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 383
 384     def __gt__(self, other):
 385         width = len(self.sig)
 386         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 387
 388     def __ge__(self, other):
 389         width = len(self.sig)
 390         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 391
 392     # no override needed: Value.__abs__ is general enough it does the job
 393     # def __abs__(self):
 394
 395     def __len__(self):
 396         return len(self.sig)
 397
 398     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 399     # def __getitem__(self, key):
 400
 401     def __new_sign(self, signed):
 402         shape = Shape(len(self), signed=signed)
 403         result = SimdSignal.like(self, shape=shape)
 404         self.m.d.comb += result.sig.eq(self.sig)
 405         return result
 406
 407     # http://bugs.libre-riscv.org/show_bug.cgi?id=719
 408     def as_unsigned(self):
 409         return self.__new_sign(False)
 410
 411     def as_signed(self):
 412         return self.__new_sign(True)
 413
 414     # useful operators
 415
 416     def bool(self):
 417         """Conversion to boolean.
 418
 419         Returns
 420         -------
 421         Value, out
 422             ``1`` if any bits are set, ``0`` otherwise.
 423         """
 424         width = len(self.sig)
 425         pa = PartitionedBool(width, self.partpoints)
 426         setattr(self.m.submodules, self.get_modname("bool"), pa)
 427         self.m.d.comb += pa.a.eq(self.sig)
 428         return pa.output
 429
 430     def any(self):
 431         """Check if any bits are ``1``.
 432
 433         Returns
 434         -------
 435         Value, out
 436             ``1`` if any bits are set, ``0`` otherwise.
 437         """
 438         return self != Const(0)  # leverage the __ne__ operator here
 439         return Operator("r|", [self])
 440
 441     def all(self):
 442         """Check if all bits are ``1``.
 443
 444         Returns
 445         -------
 446         Value, out
 447             ``1`` if all bits are set, ``0`` otherwise.
 448         """
 449         # something wrong with PartitionedAll, but self == Const(-1)"
 450         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=176#c17
 451         #width = len(self.sig)
 452         #pa = PartitionedAll(width, self.partpoints)
 453         #setattr(self.m.submodules, self.get_modname("all"), pa)
 454         #self.m.d.comb += pa.a.eq(self.sig)
 455         # return pa.output
 456         return self == Const(-1)  # leverage the __eq__ operator here
 457
 458     def xor(self):
 459         """Compute pairwise exclusive-or of every bit.
 460
 461         Returns
 462         -------
 463         Value, out
 464             ``1`` if an odd number of bits are set, ``0`` if an
 465                   even number of bits are set.
 466         """
 467         width = len(self.sig)
 468         pa = PartitionedXOR(width, self.partpoints)
 469         setattr(self.m.submodules, self.get_modname("xor"), pa)
 470         self.m.d.comb += pa.a.eq(self.sig)
 471         return pa.output
 472
 473     # not needed: Value.implies does the job
 474     # def implies(premise, conclusion):
 475
 476     # TODO. contains a Value.cast which means an override is needed (on both)
 477     # def bit_select(self, offset, width):
 478     # def word_select(self, offset, width):
 479
 480     # not needed: Value.matches, amazingly, should do the job
 481     # def matches(self, *patterns):
 482
 483     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=713
 484     def shape(self):
 485         return self.sig.shape()