src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use SimdSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  21 from ieee754.part_bits.xor import PartitionedXOR
  22 from ieee754.part_bits.bool import PartitionedBool
  23 from ieee754.part_bits.all import PartitionedAll
  24 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
  25 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
  26 from ieee754.part_mul_add.partpoints import make_partition2, PartitionPoints
  27 from ieee754.part_mux.part_mux import PMux
  28 from ieee754.part_ass.passign import PAssign
  29 from ieee754.part_cat.pcat import PCat
  30 from ieee754.part_repl.prepl import PRepl
  31 from ieee754.part.simd_scope import SimdScope
  32 from ieee754.part.layout_experiment import layout
  33 from operator import or_, xor, and_, not_
  34
  35 from nmigen import (Signal, Const, Cat)
  36 from nmigen.hdl.ast import UserValue, Shape
  37
  38
  39 def getsig(op1):
  40     if isinstance(op1, SimdSignal):
  41         op1 = op1.sig
  42     return op1
  43
  44
  45 def applyop(op1, op2, op):
  46     if isinstance(op1, SimdSignal):
  47         result = SimdSignal.like(op1)
  48     else:
  49         result = SimdSignal.like(op2)
  50     result.m.d.comb += result.sig.eq(op(getsig(op1), getsig(op2)))
  51     return result
  52
  53
  54 global modnames
  55 modnames = {}
  56 # for sub-modules to be created on-demand. Mux is done slightly
  57 # differently (has its own global)
  58 for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor', 'bool', 'all']:
  59     modnames[name] = 0
  60
  61
  62 def get_runlengths(pbit, size):
  63     res = []
  64     count = 1
  65     # identify where the 1s are, which indicates "start of a new partition"
  66     # we want a list of the lengths of all partitions
  67     for i in range(size):
  68         if pbit & (1 << i):  # it's a 1: ends old partition, starts new
  69             res.append(count)  # add partition
  70             count = 1  # start again
  71         else:
  72             count += 1
  73     # end reached, add whatever is left. could have done this by creating
  74     # "fake" extra bit on the partitions, but hey
  75     res.append(count)
  76
  77     return res
  78
  79
  80 # Prototype https://bugs.libre-soc.org/show_bug.cgi?id=713#c53
  81 # this provides a "compatibility" layer with existing SimdSignal
  82 # behaviour.  the idea is that this interface defines which "combinations"
  83 # of partition selections are relevant, and as an added bonus it says
  84 # which partition lanes are completely irrelevant (padding, blank).
  85 class PartType:  # TODO decide name
  86     def __init__(self, psig):
  87         self.psig = psig
  88
  89     def get_mask(self):
  90         return list(self.psig.partpoints.values())
  91
  92     def get_switch(self):
  93         return Cat(self.get_mask())
  94
  95     def get_cases(self):
  96         return range(1 << len(self.get_mask()))
  97
  98     def get_num_elements(self, pbit):
  99         keys = list(self.psig.partpoints.keys())
 100         return len(get_runlengths(pbit, len(keys)))
 101
 102     def get_el_range(self, pbit, el_num):
 103         """based on the element number and the current elwid/pbit (case)
 104         return the range start/end of the element within its underlying signal
 105         this function is not at all designed to be efficient.
 106         """
 107         keys = list(self.psig.partpoints.keys())
 108         runs = get_runlengths(pbit, len(keys))
 109         keys = [0] + keys + [len(self.psig.sig)]
 110         y = 0
 111         for i in range(el_num):
 112             numparts = runs[i]
 113             y += numparts
 114         numparts = runs[el_num]
 115         return range(keys[y], keys[y+numparts])
 116
 117     @property
 118     def blanklanes(self):
 119         return 0
 120
 121
 122 # this one would be an elwidth version
 123 # see https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
 124 # it requires an "adapter" which is the layout() function
 125 # where the PartitionPoints was *created* by the layout()
 126 # function and this class then "understands" the relationship
 127 # between elwidth and the PartitionPoints that were created
 128 # by layout()
 129 class ElwidPartType:  # TODO decide name
 130     def __init__(self, psig):
 131         self.psig = psig
 132
 133     def get_mask(self):
 134         return list(self.psig._shape.partpoints.values())  # i think
 135
 136     def get_switch(self):
 137         return self.psig.scope.elwid       # switch on elwid: match get_cases()
 138
 139     def get_cases(self):
 140         return self.psig._shape.bitp.keys()  # all possible values of elwid
 141
 142     @property
 143     def blanklanes(self):
 144         return self.psig.shape.blankmask
 145
 146
 147 class SimdShape(Shape):
 148     """a SIMD variant of Shape. supports:
 149     * fixed overall width with variable (maxed-out) element lengths
 150     * fixed element widths with overall size auto-determined
 151     * both fixed overall width and fixed element widths
 152
 153     naming is preserved to be compatible with Shape().
 154     """
 155
 156     def __init__(self, scope, width=None,  # this is actually widths_at_elwid
 157                  signed=False,
 158                  fixed_width=None):  # fixed overall width
 159         widths_at_elwid = width
 160         print("SimdShape width", width, "fixed_width", fixed_width)
 161         # this check is done inside layout but do it again here anyway
 162         assert fixed_width != None or widths_at_elwid != None, \
 163             "both width (widths_at_elwid) and fixed_width cannot be None"
 164         (pp, bitp, lpoints, bmask, fixed_width, lane_shapes, part_wid) = \
 165             layout(scope.elwid,
 166                    scope.vec_el_counts,
 167                    widths_at_elwid,
 168                    fixed_width)
 169         self.partpoints = pp
 170         self.bitp = bitp        # binary values for partpoints at each elwidth
 171         self.lpoints = lpoints  # layout ranges
 172         self.blankmask = bmask  # blanking mask (partitions always padding)
 173         self.partwid = part_wid  # smallest alignment start point for elements
 174
 175         # pass through the calculated width to Shape() so that when/if
 176         # objects using this Shape are downcast, they know exactly how to
 177         # get *all* bits and need know absolutely nothing about SIMD at all
 178         Shape.__init__(self, fixed_width, signed)
 179
 180
 181 class SimdSignal(UserValue):
 182     # XXX ################################################### XXX
 183     # XXX Keep these functions in the same order as ast.Value XXX
 184     # XXX ################################################### XXX
 185     def __init__(self, mask, shape=None, *args,
 186                  src_loc_at=0, fixed_width=None, **kwargs):
 187         super().__init__(src_loc_at=src_loc_at)
 188         print("SimdSignal shape", shape)
 189         # create partition points
 190         if isinstance(mask, SimdScope):  # mask parameter is a SimdScope
 191             self.scope = mask
 192             self.ptype = ElwidPartType(self)
 193             # adapt shape to a SimdShape
 194             if not isinstance(shape, SimdShape):
 195                 shape = SimdShape(self.scope, shape, fixed_width=fixed_width)
 196             self._shape = shape
 197             self.sig = Signal(shape, *args, **kwargs)
 198             # get partpoints from SimdShape
 199             self.partpoints = shape.partpoints
 200         else:
 201             self.sig = Signal(shape, *args, **kwargs)
 202             width = len(self.sig)  # get signal width
 203             if isinstance(mask, PartitionPoints):
 204                 self.partpoints = mask
 205             else:
 206                 self.partpoints = make_partition2(mask, width)
 207             self.ptype = PartType(self)
 208
 209     def set_module(self, m):
 210         self.m = m
 211
 212     def get_modname(self, category):
 213         modnames[category] += 1
 214         return "%s_%d" % (category, modnames[category])
 215
 216     @staticmethod
 217     def like(other, *args, **kwargs):
 218         """Builds a new SimdSignal with the same PartitionPoints and
 219         Signal properties as the other"""
 220         result = SimdSignal(PartitionPoints(other.partpoints))
 221         result.sig = Signal.like(other.sig, *args, **kwargs)
 222         result.m = other.m
 223         return result
 224
 225     def lower(self):
 226         return self.sig
 227
 228     # nmigen-redirected constructs (Mux, Cat, Switch, Assign)
 229
 230     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 231     # def __Part__(self, offset, width, stride=1, *, src_loc_at=0):
 232         raise NotImplementedError("TODO: implement as "
 233                                   "(self>>(offset*stride)[:width]")
 234     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 235
 236     def __Slice__(self, start, stop, *, src_loc_at=0):
 237         # NO.  Swizzled shall NOT be deployed, it violates
 238         # Project Development Practices
 239         raise NotImplementedError("TODO: need PartitionedSlice")
 240
 241     def __Repl__(self, count, *, src_loc_at=0):
 242         return PRepl(self.m, self, count, self.ptype)
 243
 244     def __Cat__(self, *args, src_loc_at=0):
 245         print("partsig cat", self, args)
 246         # TODO: need SwizzledSimdValue-aware Cat
 247         args = [self] + list(args)
 248         for sig in args:
 249             assert isinstance(sig, SimdSignal), \
 250                 "All SimdSignal.__Cat__ arguments must be " \
 251                 "a SimdSignal. %s is not." % repr(sig)
 252         return PCat(self.m, args, self.ptype)
 253
 254     def __Mux__(self, val1, val2):
 255         # print ("partsig mux", self, val1, val2)
 256         assert len(val1) == len(val2), \
 257             "SimdSignal width sources must be the same " \
 258             "val1 == %d, val2 == %d" % (len(val1), len(val2))
 259         return PMux(self.m, self.partpoints, self, val1, val2, self.ptype)
 260
 261     def __Assign__(self, val, *, src_loc_at=0):
 262         print("partsig assign", self, val)
 263         # this is a truly awful hack, outlined here:
 264         # https://bugs.libre-soc.org/show_bug.cgi?id=731#c13
 265         # during the period between constructing Simd-aware sub-modules
 266         # and the elaborate() being called on them there is a window of
 267         # opportunity to indicate which of those submodules is LHS and
 268         # which is RHS. manic laughter is permitted.  *gibber*.
 269         if hasattr(self, "_hack_submodule"):
 270             self._hack_submodule.set_lhs_mode(True)
 271         if hasattr(val, "_hack_submodule"):
 272             val._hack_submodule.set_lhs_mode(False)
 273         return PAssign(self.m, self, val, self.ptype)
 274
 275     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=458
 276     # def __Switch__(self, cases, *, src_loc=None, src_loc_at=0,
 277     #                               case_src_locs={}):
 278
 279     # no override needed, Value.__bool__ sufficient
 280     # def __bool__(self):
 281
 282     # unary ops that do not require partitioning
 283
 284     def __invert__(self):
 285         result = SimdSignal.like(self)
 286         self.m.d.comb += result.sig.eq(~self.sig)
 287         return result
 288
 289     # unary ops that require partitioning
 290
 291     def __neg__(self):
 292         z = Const(0, len(self.sig))
 293         result, _ = self.sub_op(z, self)
 294         return result
 295
 296     # binary ops that need partitioning
 297
 298     def add_op(self, op1, op2, carry):
 299         op1 = getsig(op1)
 300         op2 = getsig(op2)
 301         pa = PartitionedAdder(len(op1), self.partpoints)
 302         setattr(self.m.submodules, self.get_modname('add'), pa)
 303         comb = self.m.d.comb
 304         comb += pa.a.eq(op1)
 305         comb += pa.b.eq(op2)
 306         comb += pa.carry_in.eq(carry)
 307         result = SimdSignal.like(self)
 308         comb += result.sig.eq(pa.output)
 309         return result, pa.carry_out
 310
 311     def sub_op(self, op1, op2, carry=~0):
 312         op1 = getsig(op1)
 313         op2 = getsig(op2)
 314         pa = PartitionedAdder(len(op1), self.partpoints)
 315         setattr(self.m.submodules, self.get_modname('add'), pa)
 316         comb = self.m.d.comb
 317         comb += pa.a.eq(op1)
 318         comb += pa.b.eq(~op2)
 319         comb += pa.carry_in.eq(carry)
 320         result = SimdSignal.like(self)
 321         comb += result.sig.eq(pa.output)
 322         return result, pa.carry_out
 323
 324     def __add__(self, other):
 325         result, _ = self.add_op(self, other, carry=0)
 326         return result
 327
 328     def __radd__(self, other):
 329         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 330         result, _ = self.add_op(other, self)
 331         return result
 332
 333     def __sub__(self, other):
 334         result, _ = self.sub_op(self, other)
 335         return result
 336
 337     def __rsub__(self, other):
 338         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 339         result, _ = self.sub_op(other, self)
 340         return result
 341
 342     def __mul__(self, other):
 343         raise NotImplementedError  # too complicated at the moment
 344         return Operator("*", [self, other])
 345
 346     def __rmul__(self, other):
 347         raise NotImplementedError  # too complicated at the moment
 348         return Operator("*", [other, self])
 349
 350     # not needed: same as Value.__check_divisor
 351     # def __check_divisor(self):
 352
 353     def __mod__(self, other):
 354         raise NotImplementedError
 355         other = Value.cast(other)
 356         other.__check_divisor()
 357         return Operator("%", [self, other])
 358
 359     def __rmod__(self, other):
 360         raise NotImplementedError
 361         self.__check_divisor()
 362         return Operator("%", [other, self])
 363
 364     def __floordiv__(self, other):
 365         raise NotImplementedError
 366         other = Value.cast(other)
 367         other.__check_divisor()
 368         return Operator("//", [self, other])
 369
 370     def __rfloordiv__(self, other):
 371         raise NotImplementedError
 372         self.__check_divisor()
 373         return Operator("//", [other, self])
 374
 375     # not needed: same as Value.__check_shamt
 376     # def __check_shamt(self):
 377
 378     # TODO: detect if the 2nd operand is a Const, a Signal or a
 379     # SimdSignal.  if it's a Const or a Signal, a global shift
 380     # can occur.  if it's a SimdSignal, that's much more interesting.
 381     def ls_op(self, op1, op2, carry, shr_flag=0):
 382         op1 = getsig(op1)
 383         if isinstance(op2, Const) or isinstance(op2, Signal):
 384             scalar = True
 385             pa = PartitionedScalarShift(len(op1), self.partpoints)
 386         else:
 387             scalar = False
 388             op2 = getsig(op2)
 389             pa = PartitionedDynamicShift(len(op1), self.partpoints)
 390         # else:
 391         #   TODO: case where the *shifter* is a SimdSignal but
 392         #   the thing *being* Shifted is a scalar (Signal, expression)
 393         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 394         setattr(self.m.submodules, self.get_modname('ls'), pa)
 395         comb = self.m.d.comb
 396         if scalar:
 397             comb += pa.data.eq(op1)
 398             comb += pa.shifter.eq(op2)
 399             comb += pa.shift_right.eq(shr_flag)
 400         else:
 401             comb += pa.a.eq(op1)
 402             comb += pa.b.eq(op2)
 403             comb += pa.shift_right.eq(shr_flag)
 404         # XXX TODO: carry-in, carry-out (for arithmetic shift)
 405         #comb += pa.carry_in.eq(carry)
 406         return (pa.output, 0)
 407
 408     def __lshift__(self, other):
 409         z = Const(0, len(self.partpoints)+1)
 410         result, _ = self.ls_op(self, other, carry=z)  # TODO, carry
 411         return result
 412
 413     def __rlshift__(self, other):
 414         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 415         raise NotImplementedError
 416         return Operator("<<", [other, self])
 417
 418     def __rshift__(self, other):
 419         z = Const(0, len(self.partpoints)+1)
 420         result, _ = self.ls_op(self, other, carry=z, shr_flag=1)  # TODO, carry
 421         return result
 422
 423     def __rrshift__(self, other):
 424         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 425         raise NotImplementedError
 426         return Operator(">>", [other, self])
 427
 428     # binary ops that don't require partitioning
 429
 430     def __and__(self, other):
 431         return applyop(self, other, and_)
 432
 433     def __rand__(self, other):
 434         return applyop(other, self, and_)
 435
 436     def __or__(self, other):
 437         return applyop(self, other, or_)
 438
 439     def __ror__(self, other):
 440         return applyop(other, self, or_)
 441
 442     def __xor__(self, other):
 443         return applyop(self, other, xor)
 444
 445     def __rxor__(self, other):
 446         return applyop(other, self, xor)
 447
 448     # binary comparison ops that need partitioning
 449
 450     def _compare(self, width, op1, op2, opname, optype):
 451         # print (opname, op1, op2)
 452         pa = PartitionedEqGtGe(width, self.partpoints)
 453         setattr(self.m.submodules, self.get_modname(opname), pa)
 454         comb = self.m.d.comb
 455         comb += pa.opcode.eq(optype)  # set opcode
 456         if isinstance(op1, SimdSignal):
 457             comb += pa.a.eq(op1.sig)
 458         else:
 459             comb += pa.a.eq(op1)
 460         if isinstance(op2, SimdSignal):
 461             comb += pa.b.eq(op2.sig)
 462         else:
 463             comb += pa.b.eq(op2)
 464         return pa.output
 465
 466     def __eq__(self, other):
 467         width = len(self.sig)
 468         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 469
 470     def __ne__(self, other):
 471         width = len(self.sig)
 472         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 473         ne = Signal(eq.width)
 474         self.m.d.comb += ne.eq(~eq)
 475         return ne
 476
 477     def __lt__(self, other):
 478         width = len(self.sig)
 479         # swap operands, use gt to do lt
 480         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 481
 482     def __le__(self, other):
 483         width = len(self.sig)
 484         # swap operands, use ge to do le
 485         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 486
 487     def __gt__(self, other):
 488         width = len(self.sig)
 489         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 490
 491     def __ge__(self, other):
 492         width = len(self.sig)
 493         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 494
 495     # no override needed: Value.__abs__ is general enough it does the job
 496     # def __abs__(self):
 497
 498     def __len__(self):
 499         return len(self.sig)
 500
 501     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 502     # def __getitem__(self, key):
 503
 504     def __new_sign(self, signed):
 505         # XXX NO - SimdShape not Shape
 506         print("XXX requires SimdShape not Shape")
 507         shape = Shape(len(self), signed=signed)
 508         result = SimdSignal.like(self, shape=shape)
 509         self.m.d.comb += result.sig.eq(self.sig)
 510         return result
 511
 512     # http://bugs.libre-riscv.org/show_bug.cgi?id=719
 513     def as_unsigned(self):
 514         return self.__new_sign(False)
 515
 516     def as_signed(self):
 517         return self.__new_sign(True)
 518
 519     # useful operators
 520
 521     def bool(self):
 522         """Conversion to boolean.
 523
 524         Returns
 525         -------
 526         Value, out
 527             ``1`` if any bits are set, ``0`` otherwise.
 528         """
 529         width = len(self.sig)
 530         pa = PartitionedBool(width, self.partpoints)
 531         setattr(self.m.submodules, self.get_modname("bool"), pa)
 532         self.m.d.comb += pa.a.eq(self.sig)
 533         return pa.output
 534
 535     def any(self):
 536         """Check if any bits are ``1``.
 537
 538         Returns
 539         -------
 540         Value, out
 541             ``1`` if any bits are set, ``0`` otherwise.
 542         """
 543         return self != Const(0)  # leverage the __ne__ operator here
 544         return Operator("r|", [self])
 545
 546     def all(self):
 547         """Check if all bits are ``1``.
 548
 549         Returns
 550         -------
 551         Value, out
 552             ``1`` if all bits are set, ``0`` otherwise.
 553         """
 554         # something wrong with PartitionedAll, but self == Const(-1)"
 555         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=176#c17
 556         #width = len(self.sig)
 557         #pa = PartitionedAll(width, self.partpoints)
 558         #setattr(self.m.submodules, self.get_modname("all"), pa)
 559         #self.m.d.comb += pa.a.eq(self.sig)
 560         # return pa.output
 561         return self == Const(-1)  # leverage the __eq__ operator here
 562
 563     def xor(self):
 564         """Compute pairwise exclusive-or of every bit.
 565
 566         Returns
 567         -------
 568         Value, out
 569             ``1`` if an odd number of bits are set, ``0`` if an
 570                   even number of bits are set.
 571         """
 572         width = len(self.sig)
 573         pa = PartitionedXOR(width, self.partpoints)
 574         setattr(self.m.submodules, self.get_modname("xor"), pa)
 575         self.m.d.comb += pa.a.eq(self.sig)
 576         return pa.output
 577
 578     # not needed: Value.implies does the job
 579     # def implies(premise, conclusion):
 580
 581     # TODO. contains a Value.cast which means an override is needed (on both)
 582     # def bit_select(self, offset, width):
 583     # def word_select(self, offset, width):
 584
 585     # not needed: Value.matches, amazingly, should do the job
 586     # def matches(self, *patterns):
 587
 588     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=713
 589     def shape(self):
 590         return self.sig.shape()