src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 #from ieee754.part_cmp.equal_ortree import PartitionedEq
  21 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  22 from ieee754.part_mul_add.partpoints import make_partition
  23 from operator import or_, xor, and_, not_
  24
  25 from nmigen import (Signal,
  26                     )
  27 def applyop(op1, op2, op):
  28     if isinstance(op1, PartitionedSignal):
  29         op1 = op1.sig
  30     if isinstance(op2, PartitionedSignal):
  31         op2 = op2.sig
  32     return op(op1, op2)
  33
  34
  35 class PartitionedSignal:
  36     def __init__(self, mask, *args, **kwargs):
  37         self.sig = Signal(*args, **kwargs)
  38         width = self.sig.shape()[0] # get signal width
  39         self.partpoints = make_partition(mask, width) # create partition points
  40         self.modnames = {}
  41         for name in ['add', 'eq', 'gt', 'ge']:
  42             self.modnames[name] = 0
  43
  44     def set_module(self, m):
  45         self.m = m
  46
  47     def get_modname(self, category):
  48         self.modnames[category] += 1
  49         return "%s%d" % (category, self.modnames[category])
  50
  51     def eq(self, val):
  52         if isinstance(val, PartitionedSignal):
  53             return self.sig.eq(val.sig)
  54         return self.sig.eq(val)
  55
  56     # unary ops that do not require partitioning
  57
  58     def __invert__(self):
  59         return ~self.sig
  60
  61     # unary ops that require partitioning
  62
  63     def __neg__(self):
  64         return Operator("-", [self])
  65
  66     # binary ops that don't require partitioning
  67
  68     def __and__(self, other):
  69         return applyop(self, other, and_)
  70
  71     def __rand__(self, other):
  72         return applyop(other, self, and_)
  73
  74     def __or__(self, other):
  75         return applyop(self, other, or_)
  76
  77     def __ror__(self, other):
  78         return applyop(other, self, or_)
  79
  80     def __xor__(self, other):
  81         return applyop(self, other, xor)
  82
  83     def __rxor__(self, other):
  84         return applyop(other, self, xor)
  85
  86     # binary ops that need partitioning
  87
  88     def __add__(self, other):
  89         shape = self.sig.shape()
  90         pa = PartitionedAdder(shape[0], self.partpoints)
  91         setattr(self.m.submodules, self.get_modname('add'), pa)
  92         comb = self.m.d.comb
  93         comb += pa.a.eq(self.sig)
  94         if isinstance(other, PartitionedSignal):
  95             comb += pa.b.eq(other.sig)
  96         else:
  97             comb += pa.b.eq(other)
  98         return pa.output
  99
 100     def __radd__(self, other):
 101         return Operator("+", [other, self])
 102     def __sub__(self, other):
 103         return Operator("-", [self, other])
 104     def __rsub__(self, other):
 105         return Operator("-", [other, self])
 106
 107     def __mul__(self, other):
 108         return Operator("*", [self, other])
 109     def __rmul__(self, other):
 110         return Operator("*", [other, self])
 111
 112     def __check_divisor(self):
 113         width, signed = self.shape()
 114         if signed:
 115             # Python's division semantics and Verilog's division semantics
 116             # differ for negative divisors (Python uses div/mod, Verilog
 117             # uses quo/rem); for now, avoid the issue
 118             # completely by prohibiting such division operations.
 119             raise NotImplementedError(
 120                     "Division by a signed value is not supported")
 121     def __mod__(self, other):
 122         other = Value.cast(other)
 123         other.__check_divisor()
 124         return Operator("%", [self, other])
 125     def __rmod__(self, other):
 126         self.__check_divisor()
 127         return Operator("%", [other, self])
 128     def __floordiv__(self, other):
 129         other = Value.cast(other)
 130         other.__check_divisor()
 131         return Operator("//", [self, other])
 132     def __rfloordiv__(self, other):
 133         self.__check_divisor()
 134         return Operator("//", [other, self])
 135
 136     def __lshift__(self, other):
 137         return Operator("<<", [self, other])
 138     def __rlshift__(self, other):
 139         return Operator("<<", [other, self])
 140     def __rshift__(self, other):
 141         return Operator(">>", [self, other])
 142
 143     # binary comparison ops that need partitioning
 144
 145     def _compare(self, width, op1, op2, opname, optype):
 146         #print (opname, op1, op2)
 147         pa = PartitionedEqGtGe(width, self.partpoints)
 148         setattr(self.m.submodules, self.get_modname(opname), pa)
 149         comb = self.m.d.comb
 150         comb += pa.opcode.eq(optype) # set opcode
 151         if isinstance(op1, PartitionedSignal):
 152             comb += pa.a.eq(op1.sig)
 153         else:
 154             comb += pa.a.eq(op1)
 155         if isinstance(op2, PartitionedSignal):
 156             comb += pa.b.eq(op2.sig)
 157         else:
 158             comb += pa.b.eq(op2)
 159         return pa.output
 160
 161     def __eq__(self, other):
 162         width = self.sig.shape()[0]
 163         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 164
 165     def __ne__(self, other):
 166         width = self.sig.shape()[0]
 167         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 168         ne = Signal(eq.width)
 169         self.m.d.comb += ne.eq(~eq)
 170         return ne
 171
 172     def __gt__(self, other):
 173         width = self.sig.shape()[0]
 174         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 175
 176     def __lt__(self, other):
 177         width = self.sig.shape()[0]
 178         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 179
 180     def __ge__(self, other):
 181         width = self.sig.shape()[0]
 182         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 183
 184     def __le__(self, other):
 185         width = self.sig.shape()[0]
 186         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 187
 188     # useful operators
 189
 190     def bool(self):
 191         """Conversion to boolean.
 192
 193         Returns
 194         -------
 195         Value, out
 196             ``1`` if any bits are set, ``0`` otherwise.
 197         """
 198         return Operator("b", [self])
 199
 200     def any(self):
 201         """Check if any bits are ``1``.
 202
 203         Returns
 204         -------
 205         Value, out
 206             ``1`` if any bits are set, ``0`` otherwise.
 207         """
 208         return Operator("r|", [self])
 209
 210     def all(self):
 211         """Check if all bits are ``1``.
 212
 213         Returns
 214         -------
 215         Value, out
 216             ``1`` if all bits are set, ``0`` otherwise.
 217         """
 218         return Operator("r&", [self])
 219
 220     def xor(self):
 221         """Compute pairwise exclusive-or of every bit.
 222
 223         Returns
 224         -------
 225         Value, out
 226             ``1`` if an odd number of bits are set, ``0`` if an
 227                   even number of bits are set.
 228         """
 229         return Operator("r^", [self])
 230
 231     def implies(premise, conclusion):
 232         """Implication.
 233
 234         Returns
 235         -------
 236         Value, out
 237             ``0`` if ``premise`` is true and ``conclusion`` is not,
 238             ``1`` otherwise.
 239         """
 240         return ~premise | conclusion
 241
 242