src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 #from ieee754.part_cmp.equal_ortree import PartitionedEq
  21 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  22 from ieee754.part_mul_add.partpoints import make_partition
  23 from operator import or_, xor, and_, not_
  24
  25 from nmigen import (Signal,
  26                     )
  27
  28 def getsig(op1):
  29     if isinstance(op1, PartitionedSignal):
  30         op1 = op1.sig
  31     return op1
  32
  33 def applyop(op1, op2, op):
  34     return op(getsig(op1), getsig(op2))
  35
  36
  37 class PartitionedSignal:
  38     def __init__(self, mask, *args, **kwargs):
  39         self.sig = Signal(*args, **kwargs)
  40         width = self.sig.shape()[0] # get signal width
  41         self.partpoints = make_partition(mask, width) # create partition points
  42         self.modnames = {}
  43         for name in ['add', 'eq', 'gt', 'ge']:
  44             self.modnames[name] = 0
  45
  46     def set_module(self, m):
  47         self.m = m
  48
  49     def get_modname(self, category):
  50         self.modnames[category] += 1
  51         return "%s%d" % (category, self.modnames[category])
  52
  53     def eq(self, val):
  54         return self.sig.eq(getsig(val))
  55
  56     # unary ops that do not require partitioning
  57
  58     def __invert__(self):
  59         return ~self.sig
  60
  61     # unary ops that require partitioning
  62
  63     def __neg__(self):
  64         # TODO use PartitionedAdder for this, with a "neg" mode?
  65         return Operator("-", [self])
  66
  67     # binary ops that don't require partitioning
  68
  69     def __and__(self, other):
  70         return applyop(self, other, and_)
  71
  72     def __rand__(self, other):
  73         return applyop(other, self, and_)
  74
  75     def __or__(self, other):
  76         return applyop(self, other, or_)
  77
  78     def __ror__(self, other):
  79         return applyop(other, self, or_)
  80
  81     def __xor__(self, other):
  82         return applyop(self, other, xor)
  83
  84     def __rxor__(self, other):
  85         return applyop(other, self, xor)
  86
  87     # binary ops that need partitioning
  88
  89     # TODO: detect if the 2nd operand is a Const, a Signal or a
  90     # PartitionedSignal.  if it's a Const or a Signal, a global shift
  91     # can occur.  if it's a PartitionedSignal, that's much more interesting.
  92     def __lshift__(self, other):
  93         return Operator("<<", [self, other])
  94     def __rlshift__(self, other):
  95         return Operator("<<", [other, self])
  96     def __rshift__(self, other):
  97         return Operator(">>", [self, other])
  98     def __rrshift__(self, other):
  99         return Operator(">>", [other, self])
 100
 101     def add_op(self, op1, op2):
 102         op1 = getsig(op1)
 103         op2 = getsig(op2)
 104         shape = op1.shape()
 105         pa = PartitionedAdder(shape[0], self.partpoints)
 106         setattr(self.m.submodules, self.get_modname('add'), pa)
 107         comb = self.m.d.comb
 108         comb += pa.a.eq(op1)
 109         comb += pa.b.eq(op2)
 110         return pa.output
 111
 112     def __add__(self, other):
 113         return self.add_op(self, other)
 114
 115     def __radd__(self, other):
 116         return self.add_op(other, self)
 117
 118     def __sub__(self, other):
 119         return self.sub_op(self, other) # TODO, subop
 120     def __rsub__(self, other):
 121         return self.sub_op(other, self) # TODO, subop
 122
 123     def __mul__(self, other):
 124         return Operator("*", [self, other])
 125     def __rmul__(self, other):
 126         return Operator("*", [other, self])
 127
 128     def __check_divisor(self):
 129         width, signed = self.shape()
 130         if signed:
 131             # Python's division semantics and Verilog's division semantics
 132             # differ for negative divisors (Python uses div/mod, Verilog
 133             # uses quo/rem); for now, avoid the issue
 134             # completely by prohibiting such division operations.
 135             raise NotImplementedError(
 136                     "Division by a signed value is not supported")
 137     def __mod__(self, other):
 138         other = Value.cast(other)
 139         other.__check_divisor()
 140         return Operator("%", [self, other])
 141     def __rmod__(self, other):
 142         self.__check_divisor()
 143         return Operator("%", [other, self])
 144     def __floordiv__(self, other):
 145         other = Value.cast(other)
 146         other.__check_divisor()
 147         return Operator("//", [self, other])
 148     def __rfloordiv__(self, other):
 149         self.__check_divisor()
 150         return Operator("//", [other, self])
 151
 152     def __lshift__(self, other):
 153         return Operator("<<", [self, other])
 154     def __rlshift__(self, other):
 155         return Operator("<<", [other, self])
 156     def __rshift__(self, other):
 157         return Operator(">>", [self, other])
 158
 159     # binary comparison ops that need partitioning
 160
 161     def _compare(self, width, op1, op2, opname, optype):
 162         #print (opname, op1, op2)
 163         pa = PartitionedEqGtGe(width, self.partpoints)
 164         setattr(self.m.submodules, self.get_modname(opname), pa)
 165         comb = self.m.d.comb
 166         comb += pa.opcode.eq(optype) # set opcode
 167         if isinstance(op1, PartitionedSignal):
 168             comb += pa.a.eq(op1.sig)
 169         else:
 170             comb += pa.a.eq(op1)
 171         if isinstance(op2, PartitionedSignal):
 172             comb += pa.b.eq(op2.sig)
 173         else:
 174             comb += pa.b.eq(op2)
 175         return pa.output
 176
 177     def __eq__(self, other):
 178         width = self.sig.shape()[0]
 179         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 180
 181     def __ne__(self, other):
 182         width = self.sig.shape()[0]
 183         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 184         ne = Signal(eq.width)
 185         self.m.d.comb += ne.eq(~eq)
 186         return ne
 187
 188     def __gt__(self, other):
 189         width = self.sig.shape()[0]
 190         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 191
 192     def __lt__(self, other):
 193         width = self.sig.shape()[0]
 194         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 195
 196     def __ge__(self, other):
 197         width = self.sig.shape()[0]
 198         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 199
 200     def __le__(self, other):
 201         width = self.sig.shape()[0]
 202         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 203
 204     # useful operators
 205
 206     def bool(self):
 207         """Conversion to boolean.
 208
 209         Returns
 210         -------
 211         Value, out
 212             ``1`` if any bits are set, ``0`` otherwise.
 213         """
 214         return Operator("b", [self])
 215
 216     def any(self):
 217         """Check if any bits are ``1``.
 218
 219         Returns
 220         -------
 221         Value, out
 222             ``1`` if any bits are set, ``0`` otherwise.
 223         """
 224         return Operator("r|", [self])
 225
 226     def all(self):
 227         """Check if all bits are ``1``.
 228
 229         Returns
 230         -------
 231         Value, out
 232             ``1`` if all bits are set, ``0`` otherwise.
 233         """
 234         return Operator("r&", [self])
 235
 236     def xor(self):
 237         """Compute pairwise exclusive-or of every bit.
 238
 239         Returns
 240         -------
 241         Value, out
 242             ``1`` if an odd number of bits are set, ``0`` if an
 243                   even number of bits are set.
 244         """
 245         return Operator("r^", [self])
 246
 247     def implies(premise, conclusion):
 248         """Implication.
 249
 250         Returns
 251         -------
 252         Value, out
 253             ``0`` if ``premise`` is true and ``conclusion`` is not,
 254             ``1`` otherwise.
 255         """
 256         return ~premise | conclusion
 257
 258