src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 #from ieee754.part_cmp.equal_ortree import PartitionedEq
  21 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  22 from ieee754.part_mul_add.partpoints import make_partition
  23 from operator import or_, xor, and_, not_
  24
  25 from nmigen import (Signal,
  26                     )
  27 def applyop(op1, op2, op):
  28     if isinstance(op1, PartitionedSignal):
  29         op1 = op1.sig
  30     if isinstance(op2, PartitionedSignal):
  31         op2 = op2.sig
  32     return op(op1, op2)
  33
  34
  35 class PartitionedSignal:
  36     def __init__(self, mask, *args, **kwargs):
  37         self.sig = Signal(*args, **kwargs)
  38         width = self.sig.shape()[0] # get signal width
  39         self.partpoints = make_partition(mask, width) # create partition points
  40         self.modnames = {}
  41         for name in ['add', 'eq', 'gt', 'ge']:
  42             self.modnames[name] = 0
  43
  44     def set_module(self, m):
  45         self.m = m
  46
  47     def get_modname(self, category):
  48         self.modnames[category] += 1
  49         return "%s%d" % (category, self.modnames[category])
  50
  51     def eq(self, val):
  52         if isinstance(val, PartitionedSignal):
  53             return self.sig.eq(val.sig)
  54         return self.sig.eq(val)
  55
  56     # unary ops that do not require partitioning
  57
  58     def __invert__(self):
  59         return ~self.sig
  60
  61     # unary ops that require partitioning
  62
  63     def __neg__(self):
  64         # TODO use PartitionedAdder for this, with a "neg" mode?
  65         return Operator("-", [self])
  66
  67     # binary ops that don't require partitioning
  68
  69     def __and__(self, other):
  70         return applyop(self, other, and_)
  71
  72     def __rand__(self, other):
  73         return applyop(other, self, and_)
  74
  75     def __or__(self, other):
  76         return applyop(self, other, or_)
  77
  78     def __ror__(self, other):
  79         return applyop(other, self, or_)
  80
  81     def __xor__(self, other):
  82         return applyop(self, other, xor)
  83
  84     def __rxor__(self, other):
  85         return applyop(other, self, xor)
  86
  87     # binary ops that need partitioning
  88
  89     def __lshift__(self, other):
  90         return Operator("<<", [self, other])
  91     def __rlshift__(self, other):
  92         return Operator("<<", [other, self])
  93     def __rshift__(self, other):
  94         return Operator(">>", [self, other])
  95     def __rrshift__(self, other):
  96         return Operator(">>", [other, self])
  97
  98     def __add__(self, other):
  99         shape = self.sig.shape()
 100         pa = PartitionedAdder(shape[0], self.partpoints)
 101         setattr(self.m.submodules, self.get_modname('add'), pa)
 102         comb = self.m.d.comb
 103         comb += pa.a.eq(self.sig)
 104         if isinstance(other, PartitionedSignal):
 105             comb += pa.b.eq(other.sig)
 106         else:
 107             comb += pa.b.eq(other)
 108         return pa.output
 109
 110     def __radd__(self, other):
 111         return Operator("+", [other, self])
 112     def __sub__(self, other):
 113         return Operator("-", [self, other])
 114     def __rsub__(self, other):
 115         return Operator("-", [other, self])
 116
 117     def __mul__(self, other):
 118         return Operator("*", [self, other])
 119     def __rmul__(self, other):
 120         return Operator("*", [other, self])
 121
 122     def __check_divisor(self):
 123         width, signed = self.shape()
 124         if signed:
 125             # Python's division semantics and Verilog's division semantics
 126             # differ for negative divisors (Python uses div/mod, Verilog
 127             # uses quo/rem); for now, avoid the issue
 128             # completely by prohibiting such division operations.
 129             raise NotImplementedError(
 130                     "Division by a signed value is not supported")
 131     def __mod__(self, other):
 132         other = Value.cast(other)
 133         other.__check_divisor()
 134         return Operator("%", [self, other])
 135     def __rmod__(self, other):
 136         self.__check_divisor()
 137         return Operator("%", [other, self])
 138     def __floordiv__(self, other):
 139         other = Value.cast(other)
 140         other.__check_divisor()
 141         return Operator("//", [self, other])
 142     def __rfloordiv__(self, other):
 143         self.__check_divisor()
 144         return Operator("//", [other, self])
 145
 146     def __lshift__(self, other):
 147         return Operator("<<", [self, other])
 148     def __rlshift__(self, other):
 149         return Operator("<<", [other, self])
 150     def __rshift__(self, other):
 151         return Operator(">>", [self, other])
 152
 153     # binary comparison ops that need partitioning
 154
 155     def _compare(self, width, op1, op2, opname, optype):
 156         #print (opname, op1, op2)
 157         pa = PartitionedEqGtGe(width, self.partpoints)
 158         setattr(self.m.submodules, self.get_modname(opname), pa)
 159         comb = self.m.d.comb
 160         comb += pa.opcode.eq(optype) # set opcode
 161         if isinstance(op1, PartitionedSignal):
 162             comb += pa.a.eq(op1.sig)
 163         else:
 164             comb += pa.a.eq(op1)
 165         if isinstance(op2, PartitionedSignal):
 166             comb += pa.b.eq(op2.sig)
 167         else:
 168             comb += pa.b.eq(op2)
 169         return pa.output
 170
 171     def __eq__(self, other):
 172         width = self.sig.shape()[0]
 173         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 174
 175     def __ne__(self, other):
 176         width = self.sig.shape()[0]
 177         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 178         ne = Signal(eq.width)
 179         self.m.d.comb += ne.eq(~eq)
 180         return ne
 181
 182     def __gt__(self, other):
 183         width = self.sig.shape()[0]
 184         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 185
 186     def __lt__(self, other):
 187         width = self.sig.shape()[0]
 188         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 189
 190     def __ge__(self, other):
 191         width = self.sig.shape()[0]
 192         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 193
 194     def __le__(self, other):
 195         width = self.sig.shape()[0]
 196         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 197
 198     # useful operators
 199
 200     def bool(self):
 201         """Conversion to boolean.
 202
 203         Returns
 204         -------
 205         Value, out
 206             ``1`` if any bits are set, ``0`` otherwise.
 207         """
 208         return Operator("b", [self])
 209
 210     def any(self):
 211         """Check if any bits are ``1``.
 212
 213         Returns
 214         -------
 215         Value, out
 216             ``1`` if any bits are set, ``0`` otherwise.
 217         """
 218         return Operator("r|", [self])
 219
 220     def all(self):
 221         """Check if all bits are ``1``.
 222
 223         Returns
 224         -------
 225         Value, out
 226             ``1`` if all bits are set, ``0`` otherwise.
 227         """
 228         return Operator("r&", [self])
 229
 230     def xor(self):
 231         """Compute pairwise exclusive-or of every bit.
 232
 233         Returns
 234         -------
 235         Value, out
 236             ``1`` if an odd number of bits are set, ``0`` if an
 237                   even number of bits are set.
 238         """
 239         return Operator("r^", [self])
 240
 241     def implies(premise, conclusion):
 242         """Implication.
 243
 244         Returns
 245         -------
 246         Value, out
 247             ``0`` if ``premise`` is true and ``conclusion`` is not,
 248             ``1`` otherwise.
 249         """
 250         return ~premise | conclusion
 251
 252