src/ieee754/part_shift/test/test_shift_scalar.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from ieee754.part_mul_add.partpoints import PartitionPoints
   5
   6 from ieee754.part_shift.part_shift_scalar import \
   7     PartitionedScalarShift
   8
   9 import unittest
  10
  11 class ScalarShiftTestCase(FHDLTestCase):
  12     def get_intervals(self, signal, points):
  13         start = 0
  14         interval = []
  15         keys = list(points.keys()) + [signal.width]
  16         for key in keys:
  17             end = key
  18             interval.append(signal[start:end])
  19             start = end
  20         return interval
  21
  22     def test_scalar(self):
  23         m = Module()
  24         comb = m.d.comb
  25         mwidth = 4
  26         width = 32
  27         step = int(width/mwidth)
  28         gates = Signal(mwidth-1)
  29         points = PartitionPoints()
  30         for i in range(mwidth-1):
  31             points[(i+1)*step] = gates[i]
  32         a = Signal(width)
  33         b = Signal(width)
  34         output = Signal(width)
  35         a_intervals = self.get_intervals(a, points)
  36         output_intervals = self.get_intervals(output, points)
  37
  38         m.submodules.dut = dut = PartitionedScalarShift(width, points)
  39         comb += [dut.data.eq(a),
  40                  dut.shifter.eq(b),
  41                  output.eq(dut.output)]
  42
  43         sim = Simulator(m)
  44         def process():
  45             yield a.eq(0x01010101)
  46             yield b.eq(2)
  47             for i in range(1<<(mwidth-1)):
  48                 yield gates.eq(i)
  49                 yield Delay(1e-6)
  50                 yield Settle()
  51             yield b.eq(9)
  52             for i in range(1<<(mwidth-1)):
  53                 yield gates.eq(i)
  54                 yield Delay(1e-6)
  55                 yield Settle()
  56             yield gates.eq(1)
  57             yield Delay(1e-6)
  58             yield Settle()
  59             yield gates.eq(0)
  60             yield Delay(1e-6)
  61             yield Settle()
  62
  63
  64         sim.add_process(process)
  65         with sim.write_vcd("test.vcd", "test.gtkw", traces=[a,b,output]):
  66             sim.run()
  67
  68 if __name__ == "__main__":
  69     unittest.main()
  70
  71
  72
  73