1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from ieee754
.part_mul_add
.partpoints
import PartitionPoints
6 from ieee754
.part_shift_scalar
.part_shift_dynamic
import \
7 PartitionedDynamicShift
11 class DynamicShiftTestCase(FHDLTestCase
):
12 def get_intervals(self
, signal
, points
):
15 keys
= list(points
.keys()) + [signal
.width
]
18 interval
.append(signal
[start
:end
])
22 def test_dynamic(self
):
27 step
= int(width
/mwidth
)
28 gates
= Signal(mwidth
-1)
29 points
= PartitionPoints()
30 for i
in range(mwidth
-1):
31 points
[(i
+1)*step
] = gates
[i
]
34 output
= Signal(width
)
35 a_intervals
= self
.get_intervals(a
, points
)
36 b_intervals
= self
.get_intervals(b
, points
)
37 output_intervals
= self
.get_intervals(output
, points
)
39 m
.submodules
.dut
= dut
= PartitionedDynamicShift(width
, points
)
42 output
.eq(dut
.output
)]
46 yield a
.eq(0x01010101)
47 yield b
.eq(0x04030201)
48 for i
in range(1<<(mwidth
-1)):
60 sim
.add_process(process
)
61 with sim
.write_vcd("test.vcd", "test.gtkw", traces
=[a
,b
,output
]):
64 if __name__
== "__main__":