src/iommu/axi_rab/slice_top.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6 class slice_top(Elaboratable):
   7
   8     def __init__(self):
   9         self.int_cfg_regs = Signal()  # input
  10         self.int_rw = Signal()  # input
  11         self.int_addr_min = Signal(ADDR_WIDTH_VIRT)  # input
  12         self.int_addr_max = Signal(ADDR_WIDTH_VIRT)  # input
  13         self.multi_hit_allow = Signal()  # input
  14         self.multi_hit = Signal()  # output
  15         self.prot = Signal(N_SLICES)  # output
  16         self.hit = Signal(N_SLICES)  # output
  17         self.cache_coherent = Signal()  # output
  18         self.out_addr = Signal(ADDR_WIDTH_PHYS)  # output
  19
  20     def elaborate(self, platform=None):
  21         m = Module()
  22         return m
  23
  24
  25 # // Copyright 2018 ETH Zurich and University of Bologna.
  26 # // Copyright and related rights are licensed under the Solderpad Hardware
  27 # // License, Version 0.51 (the "License"); you may not use this file except in
  28 # // compliance with the License.  You may obtain a copy of the License at
  29 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  30 # // or agreed to in writing, software, hardware and materials distributed under
  31 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  32 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  33 # // specific language governing permissions and limitations under the License.
  34 #
  35 # module slice_top
  36 # //#(
  37 #  //  parameter N_SLICES        = 16,
  38 #  //  parameter N_REGS          = 4*N_SLICES,
  39 #   // parameter ADDR_WIDTH_PHYS = 40,
  40 #   // parameter ADDR_WIDTH_VIRT = 32
  41 #  //  )
  42 #   (
  43 #    input   logic   [N_REGS-1:0] [63:0] int_cfg_regs,
  44 #    input   logic                       int_rw,
  45 #    input   logic [ADDR_WIDTH_VIRT-1:0] int_addr_min,
  46 #    input   logic [ADDR_WIDTH_VIRT-1:0] int_addr_max,
  47 #    input   logic                       multi_hit_allow,
  48 #    output  logic                       multi_hit,
  49 #    output  logic        [N_SLICES-1:0] prot,
  50 #    output  logic        [N_SLICES-1:0] hit,
  51 #    output  logic                       cache_coherent,
  52 #    output  logic [ADDR_WIDTH_PHYS-1:0] out_addr
  53 #  );
  54 #
  55 """  #docstring_begin
  56
  57   logic first_hit;
  58
  59   genvar  i;
  60   integer j;
  61
  62   logic [ADDR_WIDTH_PHYS*N_SLICES-1:0]  slice_out_addr;
  63
  64   generate
  65     for ( i=0; i<N_SLICES; i++ )
  66       begin
  67         rab_slice
  68           #(
  69             .ADDR_WIDTH_PHYS ( ADDR_WIDTH_PHYS ),
  70             .ADDR_WIDTH_VIRT ( ADDR_WIDTH_VIRT )
  71             )
  72           u_slice
  73           (
  74             .cfg_min       ( int_cfg_regs[4*i]  [ADDR_WIDTH_VIRT-1:0]                              ),
  75             .cfg_max       ( int_cfg_regs[4*i+1][ADDR_WIDTH_VIRT-1:0]                              ),
  76             .cfg_offset    ( int_cfg_regs[4*i+2][ADDR_WIDTH_PHYS-1:0]                              ),
  77             .cfg_wen       ( int_cfg_regs[4*i+3][2]                                                ),
  78             .cfg_ren       ( int_cfg_regs[4*i+3][1]                                                ),
  79             .cfg_en        ( int_cfg_regs[4*i+3][0]                                                ),
  80             .in_trans_type ( int_rw                                                                ),
  81             .in_addr_min   ( int_addr_min                                                          ),
  82             .in_addr_max   ( int_addr_max                                                          ),
  83             .out_addr      ( slice_out_addr[ADDR_WIDTH_PHYS*i+ADDR_WIDTH_PHYS-1:ADDR_WIDTH_PHYS*i] ),
  84             .out_prot      ( prot[i]                                                               ),
  85             .out_hit       ( hit[i]                                                                )
  86           );
  87      end
  88   endgenerate
  89
  90   // In case of a multi hit, the lowest slice with a hit is selected.
  91   always_comb begin : HIT_CHECK
  92     first_hit      =  0;
  93     multi_hit      =  0;
  94     out_addr       = '0;
  95     cache_coherent =  0;
  96     for (j = 0; j < N_SLICES; j++) begin
  97       if (hit[j] == 1'b1) begin
  98         if (first_hit == 1'b1) begin
  99           if (multi_hit_allow == 1'b0) begin
 100             multi_hit = 1'b1;
 101           end
 102         end else begin
 103           first_hit       = 1'b1;
 104           out_addr        = slice_out_addr[ADDR_WIDTH_PHYS*j +: ADDR_WIDTH_PHYS];
 105           cache_coherent  = int_cfg_regs[4*j+3][3];
 106         end
 107       end
 108     end
 109   end
 110 """
 111 # endmodule
 112 #
 113 # // vim: ts=2 sw=2 sts=2 et nosmartindent autoindent foldmethod=marker
 114 #
 115 #