1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Signal
, Module
, Const
, Elaboratable
11 initial begin q=1'b0; q1=1'b1; end
15 {1'b0,1'b0}:begin q=q; q1=q1; end
16 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
17 {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
18 {1'b1,1'b1}: begin q=~q; q1=~q1; end
24 def latchregister(m
, incoming
, outgoing
, settrue
):
25 reg
= Signal
.like(incoming
) # make register same as input. reset is OK.
27 m
.d
.sync
+= reg
.eq(incoming
) # latch input into register
28 m
.d
.comb
+= outgoing
.eq(incoming
) # return input (combinatorial)
30 m
.d
.comb
+= outgoing
.eq(reg
) # return input (combinatorial)
33 class SRLatch(Elaboratable
):
34 def __init__(self
, sync
=True, llen
=1):
37 self
.s
= Signal(llen
, reset
=0)
38 self
.r
= Signal(llen
, reset
=(1<<llen
)-1) # defaults to off
39 self
.q
= Signal(llen
, reset_less
=True)
40 self
.qn
= Signal(llen
, reset_less
=True)
41 self
.qlq
= Signal(llen
, reset_less
=True)
43 def elaborate(self
, platform
):
45 q_int
= Signal(self
.llen
)
47 m
.d
.sync
+= q_int
.eq((q_int
& ~self
.r
) | self
.s
)
49 m
.d
.comb
+= self
.q
.eq(q_int
)
51 m
.d
.comb
+= self
.q
.eq((q_int
& ~self
.r
) | self
.s
)
52 m
.d
.comb
+= self
.qn
.eq(~self
.q
)
53 m
.d
.comb
+= self
.qlq
.eq(self
.q | q_int
) # useful output
58 return self
.s
, self
.r
, self
.q
, self
.qn
86 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
87 with
open("test_srlatch.il", "w") as f
:
90 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch.vcd')
92 dut
= SRLatch(sync
=False, llen
=4)
93 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
94 with
open("test_srlatch_async.il", "w") as f
:
97 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch_async.vcd')
99 if __name__
== '__main__':