1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Signal
, Module
, Elaboratable
6 class SRLatch(Elaboratable
):
7 def __init__(self
, sync
=True):
9 self
.s
= Signal(reset_less
=True)
10 self
.r
= Signal(reset_less
=True)
11 self
.q
= Signal(reset_less
=True)
12 self
.qn
= Signal(reset_less
=True)
14 def elaborate(self
, platform
):
16 q_int
= Signal(reset_less
=True)
20 m
.d
.sync
+= q_int
.eq(1)
22 m
.d
.sync
+= q_int
.eq(0)
24 m
.d
.sync
+= q_int
.eq(q_int
)
25 m
.d
.comb
+= self
.q
.eq(q_int
)
28 m
.d
.sync
+= q_int
.eq(1)
29 m
.d
.comb
+= self
.q
.eq(1)
31 m
.d
.sync
+= q_int
.eq(0)
32 m
.d
.comb
+= self
.q
.eq(0)
34 m
.d
.sync
+= q_int
.eq(q_int
)
35 m
.d
.comb
+= self
.q
.eq(q_int
)
36 m
.d
.comb
+= self
.qn
.eq(~self
.q
)
41 return self
.s
, self
.r
, self
.q
, self
.qn
69 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
70 with
open("test_srlatch.il", "w") as f
:
73 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch.vcd')
75 dut
= SRLatch(sync
=False)
76 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
77 with
open("test_srlatch_async.il", "w") as f
:
80 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch_async.vcd')
82 if __name__
== '__main__':