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26 from nmigen
import Module
, Signal
, Memory
, Mux
, Elaboratable
27 from nmigen
.tools
import bits_for
28 from nmigen
.cli
import main
29 from nmigen
.lib
.fifo
import FIFOInterface
31 # translated from https://github.com/freechipsproject/chisel3/blob/a4a29e29c3f1eed18f851dcf10bdc845571dfcb6/src/main/scala/chisel3/util/Decoupled.scala#L185 # noqa
34 class Queue(FIFOInterface
, Elaboratable
):
35 def __init__(self
, width
, depth
, fwft
=True, pipe
=False):
36 """ Queue (FIFO) with pipe mode and first-write fall-through capability
38 * :width: width of Queue data in/out
39 * :depth: queue depth. NOTE: may be set to 0 (this is ok)
40 * :fwft : first-write, fall-through mode (Chisel Queue "flow" mode)
41 * :pipe : pipe mode. NOTE: this mode can cause unanticipated
42 problems. when read is enabled, so is writeable.
43 therefore if read is enabled, the data ABSOLUTELY MUST
46 fwft mode = True basically means that the data may be transferred
47 combinatorially from input to output.
50 * level: available free space (number of unread entries)
52 din = enq_data, writable = enq_ready, we = enq_valid
53 dout = deq_data, re = deq_ready, readable = deq_valid
55 FIFOInterface
.__init
__(self
, width
, depth
, fwft
)
58 self
.level
= Signal(bits_for(depth
))
60 def elaborate(self
, platform
):
63 # set up an SRAM. XXX bug in Memory: cannot create SRAM of depth 1
64 ram
= Memory(self
.width
, self
.depth
if self
.depth
> 1 else 2)
65 m
.submodules
.ram_read
= ram_read
= ram
.read_port(synchronous
=False)
66 m
.submodules
.ram_write
= ram_write
= ram
.write_port()
69 p_ready_o
= self
.writable
73 n_valid_o
= self
.readable
78 ptr_width
= bits_for(self
.depth
- 1) if self
.depth
> 1 else 0
79 enq_ptr
= Signal(ptr_width
) # cyclic pointer to "insert" point (wrport)
80 deq_ptr
= Signal(ptr_width
) # cyclic pointer to "remove" point (rdport)
81 maybe_full
= Signal() # not reset_less (set by sync)
84 do_enq
= Signal(reset_less
=True)
85 do_deq
= Signal(reset_less
=True)
86 ptr_diff
= Signal(ptr_width
)
87 ptr_match
= Signal(reset_less
=True)
88 empty
= Signal(reset_less
=True)
89 full
= Signal(reset_less
=True)
90 enq_max
= Signal(reset_less
=True)
91 deq_max
= Signal(reset_less
=True)
93 m
.d
.comb
+= [ptr_match
.eq(enq_ptr
== deq_ptr
), # read-ptr = write-ptr
94 ptr_diff
.eq(enq_ptr
- deq_ptr
),
95 enq_max
.eq(enq_ptr
== self
.depth
- 1),
96 deq_max
.eq(deq_ptr
== self
.depth
- 1),
97 empty
.eq(ptr_match
& ~maybe_full
),
98 full
.eq(ptr_match
& maybe_full
),
99 do_enq
.eq(p_ready_o
& p_valid_i
), # write conditions ok
100 do_deq
.eq(n_ready_i
& n_valid_o
), # read conditions ok
102 # set readable and writable (NOTE: see pipe mode below)
103 n_valid_o
.eq(~empty
), # cannot read if empty!
104 p_ready_o
.eq(~full
), # cannot write if full!
106 # set up memory and connect to input and output
107 ram_write
.addr
.eq(enq_ptr
),
108 ram_write
.data
.eq(enq_data
),
109 ram_write
.en
.eq(do_enq
),
110 ram_read
.addr
.eq(deq_ptr
),
111 deq_data
.eq(ram_read
.data
) # NOTE: overridden in fwft mode
114 # under write conditions, SRAM write-pointer moves on next clock
116 m
.d
.sync
+= enq_ptr
.eq(Mux(enq_max
, 0, enq_ptr
+1))
118 # under read conditions, SRAM read-pointer moves on next clock
120 m
.d
.sync
+= deq_ptr
.eq(Mux(deq_max
, 0, deq_ptr
+1))
122 # if read-but-not-write or write-but-not-read, maybe_full set
123 with m
.If(do_enq
!= do_deq
):
124 m
.d
.sync
+= maybe_full
.eq(do_enq
)
126 # first-word fall-through: same as "flow" parameter in Chisel3 Queue
127 # basically instead of relying on the Memory characteristics (which
128 # in FPGAs do not have write-through), then when the queue is empty
129 # take the output directly from the input, i.e. *bypass* the SRAM.
130 # this done combinatorially to give the exact same characteristics
131 # as Memory "write-through"... without relying on a changing API
133 with m
.If(p_valid_i
):
134 m
.d
.comb
+= n_valid_o
.eq(1)
136 m
.d
.comb
+= deq_data
.eq(enq_data
)
137 m
.d
.comb
+= do_deq
.eq(0)
138 with m
.If(n_ready_i
):
139 m
.d
.comb
+= do_enq
.eq(0)
141 # pipe mode: if next stage says it's ready (readable), we
142 # *must* declare the input ready (writeable).
144 with m
.If(n_ready_i
):
145 m
.d
.comb
+= p_ready_o
.eq(1)
147 # set the count (available free space), optimise on power-of-two
148 if self
.depth
== 1 << ptr_width
: # is depth a power of 2
149 m
.d
.comb
+= self
.level
.eq(
150 Mux(maybe_full
& ptr_match
, self
.depth
, 0) | ptr_diff
)
152 m
.d
.comb
+= self
.level
.eq(Mux(ptr_match
,
153 Mux(maybe_full
, self
.depth
, 0),
154 Mux(deq_ptr
> enq_ptr
,
155 self
.depth
+ ptr_diff
,
161 if __name__
== "__main__":
162 reg_stage
= Queue(1, 1, pipe
=True)
163 break_ready_chain_stage
= Queue(1, 1, pipe
=True, fwft
=True)
167 def queue_ports(queue
, name_prefix
):
169 for name
in ["level",
173 port
= getattr(queue
, name
)
174 signal
= Signal(port
.shape(), name
=name_prefix
+name
)
175 m
.d
.comb
+= signal
.eq(port
)
176 retval
.append(signal
)
180 port
= getattr(queue
, name
)
181 signal
= Signal(port
.shape(), name
=name_prefix
+name
)
182 m
.d
.comb
+= port
.eq(signal
)
183 retval
.append(signal
)
186 m
.submodules
.reg_stage
= reg_stage
187 ports
+= queue_ports(reg_stage
, "reg_stage_")
188 m
.submodules
.break_ready_chain_stage
= break_ready_chain_stage
189 ports
+= queue_ports(break_ready_chain_stage
, "break_ready_chain_stage_")