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sort out subvl unit test with expected results
[openpower-isa.git] / src / openpower / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 #from nmigen.back.pysim import Settle
17 from copy import copy
18 from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from openpower.decoder.helpers import exts, gtu, ltu, undefined
21 from openpower.decoder.isa.mem import Mem, MemException
22 from openpower.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 print("addrshift")
52 print(addr)
53 print(shift)
54 x = addr.value >> shift.value
55 return SelectableInt(x, 16)
56
57 def RTS2(data):
58 return data[56:59]
59
60 def RTS1(data):
61 return data[1:3]
62
63 def RTS(data):
64 zero = SelectableInt(0, 1)
65 return selectconcat(zero, RTS2(data), RTS1(data))
66
67 def NLB(x):
68 """
69 Next Level Base
70 right shifted by 8
71 """
72 return x[4:56] # python numbering end+1
73
74 def NLS(x):
75 """
76 Next Level Size (PATS and RPDS in same bits btw)
77 NLS >= 5
78 """
79 return x[59:64] # python numbering end+1
80
81 def RPDB(x):
82 """
83 Root Page Directory Base
84 power isa docs says 4:55 investigate
85 """
86 return x[8:56] # python numbering end+1
87
88 """
89 Get Root Page
90
91 //Accessing 2nd double word of partition table (pate1)
92 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
93 // PTCR Layout
94 // ====================================================
95 // -----------------------------------------------
96 // | /// | PATB | /// | PATS |
97 // -----------------------------------------------
98 // 0 4 51 52 58 59 63
99 // PATB[4:51] holds the base address of the Partition Table,
100 // right shifted by 12 bits.
101 // This is because the address of the Partition base is
102 // 4k aligned. Hence, the lower 12bits, which are always
103 // 0 are ommitted from the PTCR.
104 //
105 // Thus, The Partition Table Base is obtained by (PATB << 12)
106 //
107 // PATS represents the partition table size right-shifted by 12 bits.
108 // The minimal size of the partition table is 4k.
109 // Thus partition table size = (1 << PATS + 12).
110 //
111 // Partition Table
112 // ====================================================
113 // 0 PATE0 63 PATE1 127
114 // |----------------------|----------------------|
115 // | | |
116 // |----------------------|----------------------|
117 // | | |
118 // |----------------------|----------------------|
119 // | | | <-- effLPID
120 // |----------------------|----------------------|
121 // .
122 // .
123 // .
124 // |----------------------|----------------------|
125 // | | |
126 // |----------------------|----------------------|
127 //
128 // The effective LPID forms the index into the Partition Table.
129 //
130 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
131 // corresponding to that partition.
132 //
133 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
134 //
135 // PATE0 Layout
136 // -----------------------------------------------
137 // |1|RTS1|/| RPDB | RTS2 | RPDS |
138 // -----------------------------------------------
139 // 0 1 2 3 4 55 56 58 59 63
140 //
141 // HR[0] : For Radix Page table, first bit should be 1.
142 // RTS1[1:2] : Gives one fragment of the Radix treesize
143 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
144 // RTS = (RTS1 << 3 + RTS2) + 31.
145 //
146 // RPDB[4:55] = Root Page Directory Base.
147 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
148 // Thus, Root page directory size = 1 << (RPDS + 3).
149 // Note: RPDS >= 5.
150 //
151 // PATE1 Layout
152 // -----------------------------------------------
153 // |///| PRTB | // | PRTS |
154 // -----------------------------------------------
155 // 0 3 4 51 52 58 59 63
156 //
157 // PRTB[4:51] = Process Table Base. This is aligned to size.
158 // PRTS[59: 63] = Process Table Size right shifted by 12.
159 // Minimal size of the process table is 4k.
160 // Process Table Size = (1 << PRTS + 12).
161 // Note: PRTS <= 24.
162 //
163 // Computing the size aligned Process Table Base:
164 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
165 // Thus, the lower 12+PRTS bits of table_base will
166 // be zero.
167
168
169 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
170 //
171 // Process Table
172 // ==========================
173 // 0 PRTE0 63 PRTE1 127
174 // |----------------------|----------------------|
175 // | | |
176 // |----------------------|----------------------|
177 // | | |
178 // |----------------------|----------------------|
179 // | | | <-- effPID
180 // |----------------------|----------------------|
181 // .
182 // .
183 // .
184 // |----------------------|----------------------|
185 // | | |
186 // |----------------------|----------------------|
187 //
188 // The effective Process id (PID) forms the index into the Process Table.
189 //
190 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
191 // corresponding to that process
192 //
193 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
194 //
195 // PRTE0 Layout
196 // -----------------------------------------------
197 // |/|RTS1|/| RPDB | RTS2 | RPDS |
198 // -----------------------------------------------
199 // 0 1 2 3 4 55 56 58 59 63
200 //
201 // RTS1[1:2] : Gives one fragment of the Radix treesize
202 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
203 // RTS = (RTS1 << 3 + RTS2) << 31,
204 // since minimal Radix Tree size is 4G.
205 //
206 // RPDB = Root Page Directory Base.
207 // RPDS = Root Page Directory Size right shifted by 3.
208 // Thus, Root page directory size = RPDS << 3.
209 // Note: RPDS >= 5.
210 //
211 // PRTE1 Layout
212 // -----------------------------------------------
213 // | /// |
214 // -----------------------------------------------
215 // 0 63
216 // All bits are reserved.
217
218
219 """
220
221 testmem = {
222
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
225 0x800000000100000b,
226
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
229 0x8000000000040009,
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0
232 # R = 1 C = 1 ATT = 0 EAA 0x7
233 0xc000000000000187,
234
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
237 0x40000000000300ad,
238 }
239
240 # this one has a 2nd level RADIX with a RPN of 0x5000
241 testmem2 = {
242
243 0x10000: # PARTITION_TABLE_2 (not implemented yet)
244 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
245 0x800000000100000b,
246
247 0x30000: # RADIX_ROOT_PTE
248 # V = 1 L = 0 NLB = 0x400 NLS = 9
249 0x8000000000040009,
250 0x40000: # RADIX_SECOND_LEVEL
251 # V = 1 L = 1 SW = 0 RPN = 0x5000
252 # R = 1 C = 1 ATT = 0 EAA 0x7
253 0xc000000005000187,
254
255 0x1000000: # PROCESS_TABLE_3
256 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
257 0x40000000000300ad,
258 }
259
260 testresult = """
261 prtbl = 1000000
262 DCACHE GET 1000000 PROCESS_TABLE_3
263 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
264 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
265 DCACHE GET 10000 PARTITION_TABLE_2
266 translated done 1 err 0 badtree 0 addr 40000 pte 0
267 """
268
269 # see qemu/target/ppc/mmu-radix64.c for reference
270 class RADIX:
271 def __init__(self, mem, caller):
272 self.mem = mem
273 self.caller = caller
274 if caller is not None:
275 print("caller")
276 print(caller)
277 self.dsisr = self.caller.spr["DSISR"]
278 self.dar = self.caller.spr["DAR"]
279 self.pidr = self.caller.spr["PIDR"]
280 self.prtbl = self.caller.spr["PRTBL"]
281 self.msr = self.caller.msr
282
283 # cached page table stuff
284 self.pgtbl0 = 0
285 self.pt0_valid = False
286 self.pgtbl3 = 0
287 self.pt3_valid = False
288
289 def __call__(self, addr, sz):
290 val = self.ld(addr.value, sz, swap=False)
291 print("RADIX memread", addr, sz, val)
292 return SelectableInt(val, sz*8)
293
294 def ld(self, address, width=8, swap=True, check_in_mem=False,
295 instr_fetch=False):
296 if instr_fetch:
297 mode = 'EXECUTE'
298 else:
299 mode = 'LOAD'
300 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
301 virt = (self.msr[MSRb.DR].value) # DR -> virtual
302 print("RADIX: ld from addr 0x%x width %d mode %s "
303 "priv %d virt %d" % (address, width, mode, priv, virt))
304
305 # virtual mode does a lookup to new address, otherwise use real addr
306 addr = SelectableInt(address, 64)
307 if virt:
308 addr = self._walk_tree(addr, mode, priv)
309 addr = addr.value
310
311 # use address to load from phys address
312 data = self.mem.ld(addr, width, swap, check_in_mem)
313 self.last_ld_addr = self.mem.last_ld_addr
314
315 # XXX set SPRs on error
316 return data
317
318 # TODO implement
319 def st(self, address, v, width=8, swap=True):
320
321 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
322 virt = (self.msr[MSRb.DR].value) # DR -> virtual
323 print("RADIX: st to addr 0x%x width %d data %x "
324 "priv %d virt %d " % (address, width, v, priv, virt))
325 mode = 'STORE'
326
327 # virtual mode does a lookup to new address, otherwise use real addr
328 addr = SelectableInt(address, 64)
329 if virt:
330 addr = self._walk_tree(addr, mode, priv)
331 addr = addr.value
332
333 # use address to store at phys address
334 res = self.mem.st(addr, v, width, swap)
335 self.last_st_addr = self.mem.last_st_addr
336
337 # XXX set SPRs on error
338 return res
339
340 def memassign(self, addr, sz, val):
341 print("memassign", addr, sz, val)
342 self.st(addr.value, val.value, sz, swap=False)
343
344 def _next_level(self, addr, check_in_mem):
345 # implement read access to mmu mem here
346
347 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
348 value = self.mem.ld(addr.value, 8, False, check_in_mem)
349 if value is None:
350 return "address lookup %x not found" % addr.value
351 # assert(value is not None, "address lookup %x not found" % addr.value)
352
353 data = SelectableInt(value, 64) # convert to SelectableInt
354 print("addr", hex(addr.value))
355 print("value", hex(value))
356 return data;
357
358 def _walk_tree(self, addr, mode, priv=1):
359 """walk tree
360
361 // vaddr 64 Bit
362 // vaddr |-----------------------------------------------------|
363 // | Unused | Used |
364 // |-----------|-----------------------------------------|
365 // | 0000000 | usefulBits = X bits (typically 52) |
366 // |-----------|-----------------------------------------|
367 // | |<--Cursize---->| |
368 // | | Index | |
369 // | | into Page | |
370 // | | Directory | |
371 // |-----------------------------------------------------|
372 // | |
373 // V |
374 // PDE |---------------------------| |
375 // |V|L|//| NLB |///|NLS| |
376 // |---------------------------| |
377 // PDE = Page Directory Entry |
378 // [0] = V = Valid Bit |
379 // [1] = L = Leaf bit. If 0, then |
380 // [4:55] = NLB = Next Level Base |
381 // right shifted by 8 |
382 // [59:63] = NLS = Next Level Size |
383 // | NLS >= 5 |
384 // | V
385 // | |--------------------------|
386 // | | usfulBits = X-Cursize |
387 // | |--------------------------|
388 // |---------------------><--NLS-->| |
389 // | Index | |
390 // | into | |
391 // | PDE | |
392 // |--------------------------|
393 // |
394 // If the next PDE obtained by |
395 // (NLB << 8 + 8 * index) is a |
396 // nonleaf, then repeat the above. |
397 // |
398 // If the next PDE is a leaf, |
399 // then Leaf PDE structure is as |
400 // follows |
401 // |
402 // |
403 // Leaf PDE |
404 // |------------------------------| |----------------|
405 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
406 // |------------------------------| |----------------|
407 // [0] = V = Valid Bit |
408 // [1] = L = Leaf Bit = 1 if leaf |
409 // PDE |
410 // [2] = Sw = Sw bit 0. |
411 // [7:51] = RPN = Real Page Number, V
412 // real_page = RPN << 12 -------------> Logical OR
413 // [52:54] = Sw Bits 1:3 |
414 // [55] = R = Reference |
415 // [56] = C = Change V
416 // [58:59] = Att = Physical Address
417 // 0b00 = Normal Memory
418 // 0b01 = SAO
419 // 0b10 = Non Idenmpotent
420 // 0b11 = Tolerant I/O
421 // [60:63] = Encoded Access
422 // Authority
423 //
424 """
425 # get sprs
426 print("_walk_tree")
427 pidr = self.caller.spr["PIDR"]
428 prtbl = self.caller.spr["PRTBL"]
429 print("PIDR", pidr)
430 print("PRTBL", prtbl)
431 p = addr[55:63]
432 print("last 8 bits ----------")
433 print
434
435 # get address of root entry
436 # need to fetch process table entry
437 # v.shift := unsigned('0' & r.prtbl(4 downto 0));
438 shift = selectconcat(SelectableInt(0, 1), NLS(prtbl))
439 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
440 print("starting with prtable, addr_next", addr_next)
441
442 assert(addr_next.bits == 64)
443 #only for first unit tests assert(addr_next.value == 0x1000000)
444
445 # read an entry from prtable, decode PTRE
446 data = self._next_level(addr_next, check_in_mem=False)
447 print("pr_table", data)
448 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
449 (rts, mbits, pgbase) = self._decode_prte(pgtbl)
450 print("pgbase", pgbase)
451
452 # WIP
453 if mbits == 0:
454 exc = MemException("invalid")
455 exc.mode = mode
456 raise exc
457
458 # mask_size := mbits(4 downto 0);
459 mask_size = mbits[0:5]
460 assert(mask_size.bits == 5)
461 print("before segment check ==========")
462 print("mask_size:", bin(mask_size.value))
463 print("mbits:", bin(mbits.value))
464
465 print("calling segment_check")
466
467 shift = self._segment_check(addr, mask_size, shift)
468 print("shift", shift)
469
470 if isinstance(addr, str):
471 return addr
472 if isinstance(shift, str):
473 return shift
474
475 old_shift = shift
476
477 mask = mask_size
478
479 # walk tree
480 while True:
481 addrsh = addrshift(addr, shift)
482 print("addrsh",addrsh)
483
484 print("calling _get_pgtable_addr")
485 print(mask) #SelectableInt(value=0x9, bits=4)
486 print(pgbase) #SelectableInt(value=0x40000, bits=56)
487 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
488 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
489 print("DONE addr_next", addr_next)
490
491 print("nextlevel----------------------------")
492 # read an entry
493 data = self._next_level(addr_next, check_in_mem=False)
494 valid = rpte_valid(data)
495 leaf = rpte_leaf(data)
496
497 print(" valid, leaf", valid, leaf)
498 if not valid:
499 exc = MemException("invalid")
500 exc.mode = mode
501 raise exc
502 if leaf:
503 print ("is leaf, checking perms")
504 ok = self._check_perms(data, priv, mode)
505 if ok == True: # data was ok, found phys address, return it?
506 paddr = self._get_pte(addrsh, addr, data)
507 print (" phys addr", hex(paddr.value))
508 return paddr
509 return ok # return the error code
510 else:
511 newlookup = self._new_lookup(data, shift, old_shift)
512 if isinstance(newlookup, str):
513 return newlookup
514 old_shift = shift # store old_shift before updating shift
515 shift, mask, pgbase = newlookup
516 print (" next level", shift, mask, pgbase)
517
518 def _get_pgbase(self, data):
519 """
520 v.pgbase := data(55 downto 8) & x"00"; NLB?
521 """
522 zero8 = SelectableInt(0, 8)
523 ret = selectconcat(data[8:56], zero8)
524 assert(ret.bits==56)
525 return ret
526
527 def _new_lookup(self, data, shift, old_shift):
528 """
529 mbits := unsigned('0' & data(4 downto 0));
530 if mbits < 5 or mbits > 16 or mbits > r.shift then
531 v.state := RADIX_FINISH;
532 v.badtree := '1'; -- throw error
533 else
534 v.shift := v.shift - mbits;
535 v.mask_size := mbits(4 downto 0);
536 v.pgbase := data(55 downto 8) & x"00"; NLB?
537 v.state := RADIX_LOOKUP; --> next level
538 end if;
539 """
540 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
541 print("mbits=", mbits)
542 if mbits < 5 or mbits > 16 or mbits > old_shift:
543 print("badtree")
544 return "badtree"
545 # reduce shift (has to be done at same bitwidth)
546 shift = shift - mbits
547 assert mbits.bits == 6
548 mask_size = mbits[2:6] # get 4 LSBs from 6-bit (using MSB0 numbering)
549 pgbase = self._get_pgbase(data)
550 return shift, mask_size, pgbase
551
552 def _decode_prte(self, data):
553 """PRTE0 Layout
554 -----------------------------------------------
555 |/|RTS1|/| RPDB | RTS2 | RPDS |
556 -----------------------------------------------
557 0 1 2 3 4 55 56 58 59 63
558 """
559 # note that SelectableInt does big-endian! so the indices
560 # below *directly* match the spec, unlike microwatt which
561 # has to turn them around (to LE)
562 rts, mbits = self._get_rts_nls(data)
563 pgbase = self._get_pgbase(data)
564
565 return (rts, mbits, pgbase)
566
567 def _get_rts_nls(self, data):
568 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
569 # RTS1 RTS2
570 rts = RTS(data)
571 assert(rts.bits == 6) # variable rts : unsigned(5 downto 0);
572 print("shift", rts)
573
574 # mbits := unsigned('0' & data(4 downto 0));
575 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
576 assert(mbits.bits == 6) #variable mbits : unsigned(5 downto 0);
577
578 return rts, mbits
579
580 def _segment_check(self, addr, mask_size, shift):
581 """checks segment valid
582 mbits := '0' & r.mask_size;
583 v.shift := r.shift + (31 - 12) - mbits;
584 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
585 if r.addr(63) /= r.addr(62) or nonzero = '1' then
586 v.state := RADIX_FINISH;
587 v.segerror := '1';
588 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
589 v.state := RADIX_FINISH;
590 v.badtree := '1';
591 else
592 v.state := RADIX_LOOKUP;
593 """
594 # note that SelectableInt does big-endian! so the indices
595 # below *directly* match the spec, unlike microwatt which
596 # has to turn them around (to LE)
597 mbits = selectconcat(SelectableInt(0,1), mask_size)
598 mask = genmask(shift, 44)
599 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
600 print ("RADIX _segment_check nonzero", bin(nonzero.value))
601 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
602 if addr[0] != addr[1] or nonzero != 0:
603 return "segerror"
604 limit = shift + (31 - 12)
605 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
606 return "badtree"
607 new_shift = SelectableInt(limit.value - mbits.value, shift.bits)
608 # TODO verify that returned result is correct
609 return new_shift
610
611 def _check_perms(self, data, priv, mode):
612 """check page permissions
613 // Leaf PDE |
614 // |------------------------------| |----------------|
615 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
616 // |------------------------------| |----------------|
617 // [0] = V = Valid Bit |
618 // [1] = L = Leaf Bit = 1 if leaf |
619 // PDE |
620 // [2] = Sw = Sw bit 0. |
621 // [7:51] = RPN = Real Page Number, V
622 // real_page = RPN << 12 -------------> Logical OR
623 // [52:54] = Sw Bits 1:3 |
624 // [55] = R = Reference |
625 // [56] = C = Change V
626 // [58:59] = Att = Physical Address
627 // 0b00 = Normal Memory
628 // 0b01 = SAO
629 // 0b10 = Non Idenmpotent
630 // 0b11 = Tolerant I/O
631 // [60:63] = Encoded Access
632 // Authority
633 //
634 -- test leaf bit
635 -- check permissions and RC bits
636 perm_ok := '0';
637 if r.priv = '1' or data(3) = '0' then
638 if r.iside = '0' then
639 perm_ok := data(1) or (data(2) and not r.store);
640 else
641 -- no IAMR, so no KUEP support for now
642 -- deny execute permission if cache inhibited
643 perm_ok := data(0) and not data(5);
644 end if;
645 end if;
646 rc_ok := data(8) and (data(7) or not r.store);
647 if perm_ok = '1' and rc_ok = '1' then
648 v.state := RADIX_LOAD_TLB;
649 else
650 v.state := RADIX_FINISH;
651 v.perm_err := not perm_ok;
652 -- permission error takes precedence over RC error
653 v.rc_error := perm_ok;
654 end if;
655 """
656 # decode mode into something that matches microwatt equivalent code
657 instr_fetch, store = 0, 0
658 if mode == 'STORE':
659 store = 1
660 if mode == 'EXECUTE':
661 inst_fetch = 1
662
663 # check permissions and RC bits
664 perm_ok = 0
665 if priv == 1 or data[60] == 0:
666 if instr_fetch == 0:
667 perm_ok = data[62] | (data[61] & (store == 0))
668 # no IAMR, so no KUEP support for now
669 # deny execute permission if cache inhibited
670 perm_ok = data[63] & ~data[58]
671 rc_ok = data[55] & (data[56] | (store == 0))
672 if perm_ok == 1 and rc_ok == 1:
673 return True
674
675 return "perm_err" if perm_ok == 0 else "rc_err"
676
677 def _get_prtable_addr(self, shift, prtbl, addr, pid):
678 """
679 if r.addr(63) = '1' then
680 effpid := x"00000000";
681 else
682 effpid := r.pid;
683 end if;
684 x"00" & r.prtbl(55 downto 36) &
685 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
686 (effpid(31 downto 8) and finalmask(23 downto 0))) &
687 effpid(7 downto 0) & "0000";
688 """
689 finalmask = genmask(shift, 44)
690 finalmask24 = finalmask[20:44]
691 print ("_get_prtable_addr", shift, prtbl, addr, pid,
692 bin(finalmask24.value))
693 if addr[0].value == 1:
694 effpid = SelectableInt(0, 32)
695 else:
696 effpid = pid #self.pid # TODO, check on this
697 zero8 = SelectableInt(0, 8)
698 zero4 = SelectableInt(0, 4)
699 res = selectconcat(zero8,
700 prtbl[8:28], #
701 (prtbl[28:52] & ~finalmask24) | #
702 (effpid[0:24] & finalmask24), #
703 effpid[24:32],
704 zero4
705 )
706 return res
707
708 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
709 """
710 x"00" & r.pgbase(55 downto 19) &
711 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
712 "000";
713 """
714 print("pgbase",pgbase)
715 assert(pgbase.bits==56)
716 mask16 = genmask(mask_size+5, 16)
717 zero8 = SelectableInt(0, 8)
718 zero3 = SelectableInt(0, 3)
719 res = selectconcat(zero8,
720 pgbase[0:37],
721 (pgbase[37:53] & ~mask16) |
722 (addrsh & mask16),
723 zero3
724 )
725 return res
726
727 def _get_pte(self, shift, addr, pde):
728 """
729 x"00" &
730 ((r.pde(55 downto 12) and not finalmask) or
731 (r.addr(55 downto 12) and finalmask))
732 & r.pde(11 downto 0);
733 """
734 shift.value = 12
735 finalmask = genmask(shift, 44)
736 zero8 = SelectableInt(0, 8)
737 rpn = pde[8:52] # RPN = Real Page Number
738 abits = addr[8:52] # non-masked address bits
739 print(" get_pte RPN", hex(rpn.value))
740 print(" abits", hex(abits.value))
741 print(" shift", shift.value)
742 print(" finalmask", bin(finalmask.value))
743 res = selectconcat(zero8,
744 (rpn & ~finalmask) | #
745 (abits & finalmask), #
746 addr[52:64],
747 )
748 return res
749
750
751 class TestRadixMMU(unittest.TestCase):
752
753 def test_genmask(self):
754 shift = SelectableInt(5, 6)
755 mask = genmask(shift, 43)
756 print (" mask", bin(mask.value))
757
758 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
759
760 def test_RPDB(self):
761 inp = SelectableInt(0x40000000000300ad, 64)
762
763 rtdb = RPDB(inp)
764 print("rtdb",rtdb,bin(rtdb.value))
765 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
766
767 result = selectconcat(rtdb,SelectableInt(0,8))
768 print("result",result)
769
770 def test_get_pgtable_addr(self):
771
772 mem = None
773 caller = None
774 dut = RADIX(mem, caller)
775
776 mask_size=4
777 pgbase = SelectableInt(0,56)
778 addrsh = SelectableInt(0,16)
779 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
780 print("ret=", ret)
781 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
782
783 def test_walk_tree_1(self):
784
785 # test address as in
786 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
787 testaddr = 0x1000
788 expected = 0x1000
789
790 # starting prtbl
791 prtbl = 0x1000000
792
793 # set up dummy minimal ISACaller
794 spr = {'DSISR': SelectableInt(0, 64),
795 'DAR': SelectableInt(0, 64),
796 'PIDR': SelectableInt(0, 64),
797 'PRTBL': SelectableInt(prtbl, 64)
798 }
799 # set problem state == 0 (other unit tests, set to 1)
800 msr = SelectableInt(0, 64)
801 msr[MSRb.PR] = 0
802 class ISACaller: pass
803 caller = ISACaller()
804 caller.spr = spr
805 caller.msr = msr
806
807 shift = SelectableInt(5, 6)
808 mask = genmask(shift, 43)
809 print (" mask", bin(mask.value))
810
811 mem = Mem(row_bytes=8, initial_mem=testmem)
812 mem = RADIX(mem, caller)
813 # -----------------------------------------------
814 # |/|RTS1|/| RPDB | RTS2 | RPDS |
815 # -----------------------------------------------
816 # |0|1 2|3|4 55|56 58|59 63|
817 data = SelectableInt(0, 64)
818 data[1:3] = 0b01
819 data[56:59] = 0b11
820 data[59:64] = 0b01101 # mask
821 data[55] = 1
822 (rts, mbits, pgbase) = mem._decode_prte(data)
823 print (" rts", bin(rts.value), rts.bits)
824 print (" mbits", bin(mbits.value), mbits.bits)
825 print (" pgbase", hex(pgbase.value), pgbase.bits)
826 addr = SelectableInt(0x1000, 64)
827 check = mem._segment_check(addr, mbits, shift)
828 print (" segment check", check)
829
830 print("walking tree")
831 addr = SelectableInt(testaddr,64)
832 # pgbase = None
833 mode = None
834 #mbits = None
835 shift = rts
836 result = mem._walk_tree(addr, mode)
837 print(" walking tree result", result)
838 print("should be", testresult)
839 self.assertEqual(result.value, expected,
840 "expected 0x%x got 0x%x" % (expected,
841 result.value))
842
843 def test_walk_tree_2(self):
844
845 # test address slightly different
846 testaddr = 0x1101
847 expected = 0x5001101
848
849 # starting prtbl
850 prtbl = 0x1000000
851
852 # set up dummy minimal ISACaller
853 spr = {'DSISR': SelectableInt(0, 64),
854 'DAR': SelectableInt(0, 64),
855 'PIDR': SelectableInt(0, 64),
856 'PRTBL': SelectableInt(prtbl, 64)
857 }
858 # set problem state == 0 (other unit tests, set to 1)
859 msr = SelectableInt(0, 64)
860 msr[MSRb.PR] = 0
861 class ISACaller: pass
862 caller = ISACaller()
863 caller.spr = spr
864 caller.msr = msr
865
866 shift = SelectableInt(5, 6)
867 mask = genmask(shift, 43)
868 print (" mask", bin(mask.value))
869
870 mem = Mem(row_bytes=8, initial_mem=testmem2)
871 mem = RADIX(mem, caller)
872 # -----------------------------------------------
873 # |/|RTS1|/| RPDB | RTS2 | RPDS |
874 # -----------------------------------------------
875 # |0|1 2|3|4 55|56 58|59 63|
876 data = SelectableInt(0, 64)
877 data[1:3] = 0b01
878 data[56:59] = 0b11
879 data[59:64] = 0b01101 # mask
880 data[55] = 1
881 (rts, mbits, pgbase) = mem._decode_prte(data)
882 print (" rts", bin(rts.value), rts.bits)
883 print (" mbits", bin(mbits.value), mbits.bits)
884 print (" pgbase", hex(pgbase.value), pgbase.bits)
885 addr = SelectableInt(0x1000, 64)
886 check = mem._segment_check(addr, mbits, shift)
887 print (" segment check", check)
888
889 print("walking tree")
890 addr = SelectableInt(testaddr,64)
891 # pgbase = None
892 mode = None
893 #mbits = None
894 shift = rts
895 result = mem._walk_tree(addr, mode)
896 print(" walking tree result", result)
897 print("should be", testresult)
898 self.assertEqual(result.value, expected,
899 "expected 0x%x got 0x%x" % (expected,
900 result.value))
901
902
903 if __name__ == '__main__':
904 unittest.main()