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pysvp64db: fix traversal
[openpower-isa.git] / src / openpower / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 #from nmigen.sim import Settle
17 from copy import copy
18 from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from openpower.decoder.helpers import exts, gtu, ltu, undefined
21 from openpower.decoder.isa.mem import Mem, MemException
22 from openpower.consts import MSRb # big-endian (PowerISA versions)
23 from openpower.util import log
24
25 import math
26 import sys
27 import unittest
28
29 # very quick, TODO move to SelectableInt utils later
30 def genmask(shift, size):
31 res = SelectableInt(0, size)
32 for i in range(size):
33 if i < shift:
34 res[size-1-i] = SelectableInt(1, 1)
35 return res
36
37 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
38 # MSB is indexed **LOWEST** (sigh)
39 # from gem5 radixwalk.hh
40 # Bitfield<63> valid; 64 - (63 + 1) = 0
41 # Bitfield<62> leaf; 64 - (62 + 1) = 1
42
43 def rpte_valid(r):
44 return bool(r[0])
45
46 def rpte_leaf(r):
47 return bool(r[1])
48
49 ## Shift address bits 61--12 right by 0--47 bits and
50 ## supply the least significant 16 bits of the result.
51 def addrshift(addr,shift):
52 log("addrshift")
53 log(addr)
54 log(shift)
55 x = addr.value >> shift.value
56 return SelectableInt(x, 16)
57
58 def RTS2(data):
59 return data[56:59]
60
61 def RTS1(data):
62 return data[1:3]
63
64 def RTS(data):
65 zero = SelectableInt(0, 1)
66 return selectconcat(zero, RTS2(data), RTS1(data))
67
68 def NLB(x):
69 """
70 Next Level Base
71 right shifted by 8
72 """
73 return x[4:56] # python numbering end+1
74
75 def NLS(x):
76 """
77 Next Level Size (PATS and RPDS in same bits btw)
78 NLS >= 5
79 """
80 return x[59:64] # python numbering end+1
81
82 def RPDB(x):
83 """
84 Root Page Directory Base
85 power isa docs says 4:55 investigate
86 """
87 return x[8:56] # python numbering end+1
88
89 """
90 Get Root Page
91
92 //Accessing 2nd double word of partition table (pate1)
93 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
94 // PTCR Layout
95 // ====================================================
96 // -----------------------------------------------
97 // | /// | PATB | /// | PATS |
98 // -----------------------------------------------
99 // 0 4 51 52 58 59 63
100 // PATB[4:51] holds the base address of the Partition Table,
101 // right shifted by 12 bits.
102 // This is because the address of the Partition base is
103 // 4k aligned. Hence, the lower 12bits, which are always
104 // 0 are ommitted from the PTCR.
105 //
106 // Thus, The Partition Table Base is obtained by (PATB << 12)
107 //
108 // PATS represents the partition table size right-shifted by 12 bits.
109 // The minimal size of the partition table is 4k.
110 // Thus partition table size = (1 << PATS + 12).
111 //
112 // Partition Table
113 // ====================================================
114 // 0 PATE0 63 PATE1 127
115 // |----------------------|----------------------|
116 // | | |
117 // |----------------------|----------------------|
118 // | | |
119 // |----------------------|----------------------|
120 // | | | <-- effLPID
121 // |----------------------|----------------------|
122 // .
123 // .
124 // .
125 // |----------------------|----------------------|
126 // | | |
127 // |----------------------|----------------------|
128 //
129 // The effective LPID forms the index into the Partition Table.
130 //
131 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
132 // corresponding to that partition.
133 //
134 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
135 //
136 // PATE0 Layout
137 // -----------------------------------------------
138 // |1|RTS1|/| RPDB | RTS2 | RPDS |
139 // -----------------------------------------------
140 // 0 1 2 3 4 55 56 58 59 63
141 //
142 // HR[0] : For Radix Page table, first bit should be 1.
143 // RTS1[1:2] : Gives one fragment of the Radix treesize
144 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
145 // RTS = (RTS1 << 3 + RTS2) + 31.
146 //
147 // RPDB[4:55] = Root Page Directory Base.
148 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
149 // Thus, Root page directory size = 1 << (RPDS + 3).
150 // Note: RPDS >= 5.
151 //
152 // PATE1 Layout
153 // -----------------------------------------------
154 // |///| PRTB | // | PRTS |
155 // -----------------------------------------------
156 // 0 3 4 51 52 58 59 63
157 //
158 // PRTB[4:51] = Process Table Base. This is aligned to size.
159 // PRTS[59: 63] = Process Table Size right shifted by 12.
160 // Minimal size of the process table is 4k.
161 // Process Table Size = (1 << PRTS + 12).
162 // Note: PRTS <= 24.
163 //
164 // Computing the size aligned Process Table Base:
165 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
166 // Thus, the lower 12+PRTS bits of table_base will
167 // be zero.
168
169
170 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
171 //
172 // Process Table
173 // ==========================
174 // 0 PRTE0 63 PRTE1 127
175 // |----------------------|----------------------|
176 // | | |
177 // |----------------------|----------------------|
178 // | | |
179 // |----------------------|----------------------|
180 // | | | <-- effPID
181 // |----------------------|----------------------|
182 // .
183 // .
184 // .
185 // |----------------------|----------------------|
186 // | | |
187 // |----------------------|----------------------|
188 //
189 // The effective Process id (PID) forms the index into the Process Table.
190 //
191 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
192 // corresponding to that process
193 //
194 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
195 //
196 // PRTE0 Layout
197 // -----------------------------------------------
198 // |/|RTS1|/| RPDB | RTS2 | RPDS |
199 // -----------------------------------------------
200 // 0 1 2 3 4 55 56 58 59 63
201 //
202 // RTS1[1:2] : Gives one fragment of the Radix treesize
203 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
204 // RTS = (RTS1 << 3 + RTS2) << 31,
205 // since minimal Radix Tree size is 4G.
206 //
207 // RPDB = Root Page Directory Base.
208 // RPDS = Root Page Directory Size right shifted by 3.
209 // Thus, Root page directory size = RPDS << 3.
210 // Note: RPDS >= 5.
211 //
212 // PRTE1 Layout
213 // -----------------------------------------------
214 // | /// |
215 // -----------------------------------------------
216 // 0 63
217 // All bits are reserved.
218
219
220 """
221
222 testmem = {
223
224 0x10000: # PARTITION_TABLE_2 (not implemented yet)
225 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
226 0x800000000100000b,
227
228 0x30000: # RADIX_ROOT_PTE
229 # V = 1 L = 0 NLB = 0x400 NLS = 9
230 0x8000000000040009,
231 0x40000: # RADIX_SECOND_LEVEL
232 # V = 1 L = 1 SW = 0 RPN = 0
233 # R = 1 C = 1 ATT = 0 EAA 0x7
234 0xc000000000000187,
235
236 0x1000000: # PROCESS_TABLE_3
237 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
238 0x40000000000300ad,
239 }
240
241 # this one has a 2nd level RADIX with a RPN of 0x5000
242 testmem2 = {
243
244 0x10000: # PARTITION_TABLE_2 (not implemented yet)
245 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
246 0x800000000100000b,
247
248 0x30000: # RADIX_ROOT_PTE
249 # V = 1 L = 0 NLB = 0x400 NLS = 9
250 0x8000000000040009,
251 0x40000: # RADIX_SECOND_LEVEL
252 # V = 1 L = 1 SW = 0 RPN = 0x5000
253 # R = 1 C = 1 ATT = 0 EAA 0x7
254 0xc000000005000187,
255
256 0x1000000: # PROCESS_TABLE_3
257 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
258 0x40000000000300ad,
259 }
260
261 testresult = """
262 prtbl = 1000000
263 DCACHE GET 1000000 PROCESS_TABLE_3
264 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
265 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
266 DCACHE GET 10000 PARTITION_TABLE_2
267 translated done 1 err 0 badtree 0 addr 40000 pte 0
268 """
269
270 # see qemu/target/ppc/mmu-radix64.c for reference
271 class RADIX:
272 def __init__(self, mem, caller):
273 self.mem = mem
274 self.caller = caller
275 if caller is not None:
276 log("caller")
277 log(caller)
278 self.dsisr = self.caller.spr["DSISR"]
279 self.dar = self.caller.spr["DAR"]
280 self.pidr = self.caller.spr["PIDR"]
281 self.prtbl = self.caller.spr["PRTBL"]
282 self.msr = self.caller.msr
283
284 # cached page table stuff
285 self.pgtbl0 = 0
286 self.pt0_valid = False
287 self.pgtbl3 = 0
288 self.pt3_valid = False
289
290 def __call__(self, addr, sz):
291 val = self.ld(addr.value, sz, swap=False)
292 log("RADIX memread", addr, sz, val)
293 return SelectableInt(val, sz*8)
294
295 def ld(self, address, width=8, swap=True, check_in_mem=False,
296 instr_fetch=False):
297 if instr_fetch:
298 mode = 'EXECUTE'
299 else:
300 mode = 'LOAD'
301 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
302 virt = (self.msr[MSRb.DR].value) # DR -> virtual
303 log("RADIX: ld from addr 0x%x width %d mode %s "
304 "priv %d virt %d" % (address, width, mode, priv, virt))
305
306 # virtual mode does a lookup to new address, otherwise use real addr
307 addr = SelectableInt(address, 64)
308 if virt:
309 addr = self._walk_tree(addr, mode, priv)
310 addr = addr.value
311
312 # use address to load from phys address
313 data = self.mem.ld(addr, width, swap, check_in_mem)
314 self.last_ld_addr = self.mem.last_ld_addr
315
316 # XXX set SPRs on error
317 return data
318
319 # TODO implement
320 def st(self, address, v, width=8, swap=True):
321
322 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
323 virt = (self.msr[MSRb.DR].value) # DR -> virtual
324 log("RADIX: st to addr 0x%x width %d data %x "
325 "priv %d virt %d " % (address, width, v, priv, virt))
326 mode = 'STORE'
327
328 # virtual mode does a lookup to new address, otherwise use real addr
329 addr = SelectableInt(address, 64)
330 if virt:
331 addr = self._walk_tree(addr, mode, priv)
332 addr = addr.value
333
334 # use address to store at phys address
335 res = self.mem.st(addr, v, width, swap)
336 self.last_st_addr = self.mem.last_st_addr
337
338 # XXX set SPRs on error
339 return res
340
341 def memassign(self, addr, sz, val):
342 log("memassign", addr, sz, val)
343 self.st(addr.value, val.value, sz, swap=False)
344
345 def _next_level(self, addr, check_in_mem):
346 # implement read access to mmu mem here
347
348 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
349 value = self.mem.ld(addr.value, 8, False, check_in_mem)
350 if value is None:
351 return "address lookup %x not found" % addr.value
352 # assert(value is not None, "address lookup %x not found" % addr.value)
353
354 data = SelectableInt(value, 64) # convert to SelectableInt
355 log("addr", hex(addr.value))
356 log("value", hex(value))
357 return data;
358
359 def _walk_tree(self, addr, mode, priv=1):
360 """walk tree
361
362 // vaddr 64 Bit
363 // vaddr |-----------------------------------------------------|
364 // | Unused | Used |
365 // |-----------|-----------------------------------------|
366 // | 0000000 | usefulBits = X bits (typically 52) |
367 // |-----------|-----------------------------------------|
368 // | |<--Cursize---->| |
369 // | | Index | |
370 // | | into Page | |
371 // | | Directory | |
372 // |-----------------------------------------------------|
373 // | |
374 // V |
375 // PDE |---------------------------| |
376 // |V|L|//| NLB |///|NLS| |
377 // |---------------------------| |
378 // PDE = Page Directory Entry |
379 // [0] = V = Valid Bit |
380 // [1] = L = Leaf bit. If 0, then |
381 // [4:55] = NLB = Next Level Base |
382 // right shifted by 8 |
383 // [59:63] = NLS = Next Level Size |
384 // | NLS >= 5 |
385 // | V
386 // | |--------------------------|
387 // | | usfulBits = X-Cursize |
388 // | |--------------------------|
389 // |---------------------><--NLS-->| |
390 // | Index | |
391 // | into | |
392 // | PDE | |
393 // |--------------------------|
394 // |
395 // If the next PDE obtained by |
396 // (NLB << 8 + 8 * index) is a |
397 // nonleaf, then repeat the above. |
398 // |
399 // If the next PDE is a leaf, |
400 // then Leaf PDE structure is as |
401 // follows |
402 // |
403 // |
404 // Leaf PDE |
405 // |------------------------------| |----------------|
406 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
407 // |------------------------------| |----------------|
408 // [0] = V = Valid Bit |
409 // [1] = L = Leaf Bit = 1 if leaf |
410 // PDE |
411 // [2] = Sw = Sw bit 0. |
412 // [7:51] = RPN = Real Page Number, V
413 // real_page = RPN << 12 -------------> Logical OR
414 // [52:54] = Sw Bits 1:3 |
415 // [55] = R = Reference |
416 // [56] = C = Change V
417 // [58:59] = Att = Physical Address
418 // 0b00 = Normal Memory
419 // 0b01 = SAO
420 // 0b10 = Non Idenmpotent
421 // 0b11 = Tolerant I/O
422 // [60:63] = Encoded Access
423 // Authority
424 //
425 """
426 # get sprs
427 log("_walk_tree")
428 pidr = self.caller.spr["PIDR"]
429 prtbl = self.caller.spr["PRTBL"]
430 log("PIDR", pidr)
431 log("PRTBL", prtbl)
432 p = addr[55:63]
433 log("last 8 bits ----------")
434 log()
435
436 # get address of root entry
437 # need to fetch process table entry
438 # v.shift := unsigned('0' & r.prtbl(4 downto 0));
439 shift = selectconcat(SelectableInt(0, 1), NLS(prtbl))
440 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
441 log("starting with prtable, addr_next", addr_next)
442
443 assert(addr_next.bits == 64)
444 #only for first unit tests assert(addr_next.value == 0x1000000)
445
446 # read an entry from prtable, decode PTRE
447 data = self._next_level(addr_next, check_in_mem=False)
448 log("pr_table", data)
449 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
450 (rts, mbits, pgbase) = self._decode_prte(pgtbl)
451 log("pgbase", pgbase)
452
453 # WIP
454 if mbits == 0:
455 exc = MemException("invalid")
456 exc.mode = mode
457 raise exc
458
459 # mask_size := mbits(4 downto 0);
460 mask_size = mbits[0:5]
461 assert(mask_size.bits == 5)
462 log("before segment check ==========")
463 log("mask_size:", bin(mask_size.value))
464 log("mbits:", bin(mbits.value))
465
466 log("calling segment_check")
467
468 shift = self._segment_check(addr, mask_size, shift)
469 log("shift", shift)
470
471 if isinstance(addr, str):
472 return addr
473 if isinstance(shift, str):
474 return shift
475
476 old_shift = shift
477
478 mask = mask_size
479
480 # walk tree
481 while True:
482 addrsh = addrshift(addr, shift)
483 log("addrsh",addrsh)
484
485 log("calling _get_pgtable_addr")
486 log(mask) #SelectableInt(value=0x9, bits=4)
487 log(pgbase) #SelectableInt(value=0x40000, bits=56)
488 log(shift) #SelectableInt(value=0x4, bits=16) #FIXME
489 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
490 log("DONE addr_next", addr_next)
491
492 log("nextlevel----------------------------")
493 # read an entry
494 data = self._next_level(addr_next, check_in_mem=False)
495 valid = rpte_valid(data)
496 leaf = rpte_leaf(data)
497
498 log(" valid, leaf", valid, leaf)
499 if not valid:
500 exc = MemException("invalid")
501 exc.mode = mode
502 raise exc
503 if leaf:
504 log ("is leaf, checking perms")
505 ok = self._check_perms(data, priv, mode)
506 if ok == True: # data was ok, found phys address, return it?
507 paddr = self._get_pte(addrsh, addr, data)
508 log (" phys addr", hex(paddr.value))
509 return paddr
510 return ok # return the error code
511 else:
512 newlookup = self._new_lookup(data, shift, old_shift)
513 if isinstance(newlookup, str):
514 return newlookup
515 old_shift = shift # store old_shift before updating shift
516 shift, mask, pgbase = newlookup
517 log (" next level", shift, mask, pgbase)
518
519 def _get_pgbase(self, data):
520 """
521 v.pgbase := data(55 downto 8) & x"00"; NLB?
522 """
523 zero8 = SelectableInt(0, 8)
524 ret = selectconcat(data[8:56], zero8)
525 assert(ret.bits==56)
526 return ret
527
528 def _new_lookup(self, data, shift, old_shift):
529 """
530 mbits := unsigned('0' & data(4 downto 0));
531 if mbits < 5 or mbits > 16 or mbits > r.shift then
532 v.state := RADIX_FINISH;
533 v.badtree := '1'; -- throw error
534 else
535 v.shift := v.shift - mbits;
536 v.mask_size := mbits(4 downto 0);
537 v.pgbase := data(55 downto 8) & x"00"; NLB?
538 v.state := RADIX_LOOKUP; --> next level
539 end if;
540 """
541 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
542 log("mbits=", mbits)
543 if mbits < 5 or mbits > 16 or mbits > old_shift:
544 log("badtree")
545 return "badtree"
546 # reduce shift (has to be done at same bitwidth)
547 shift = shift - mbits
548 assert mbits.bits == 6
549 mask_size = mbits[2:6] # get 4 LSBs from 6-bit (using MSB0 numbering)
550 pgbase = self._get_pgbase(data)
551 return shift, mask_size, pgbase
552
553 def _decode_prte(self, data):
554 """PRTE0 Layout
555 -----------------------------------------------
556 |/|RTS1|/| RPDB | RTS2 | RPDS |
557 -----------------------------------------------
558 0 1 2 3 4 55 56 58 59 63
559 """
560 # note that SelectableInt does big-endian! so the indices
561 # below *directly* match the spec, unlike microwatt which
562 # has to turn them around (to LE)
563 rts, mbits = self._get_rts_nls(data)
564 pgbase = self._get_pgbase(data)
565
566 return (rts, mbits, pgbase)
567
568 def _get_rts_nls(self, data):
569 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
570 # RTS1 RTS2
571 rts = RTS(data)
572 assert(rts.bits == 6) # variable rts : unsigned(5 downto 0);
573 log("shift", rts)
574
575 # mbits := unsigned('0' & data(4 downto 0));
576 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
577 assert(mbits.bits == 6) #variable mbits : unsigned(5 downto 0);
578
579 return rts, mbits
580
581 def _segment_check(self, addr, mask_size, shift):
582 """checks segment valid
583 mbits := '0' & r.mask_size;
584 v.shift := r.shift + (31 - 12) - mbits;
585 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
586 if r.addr(63) /= r.addr(62) or nonzero = '1' then
587 v.state := RADIX_FINISH;
588 v.segerror := '1';
589 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
590 v.state := RADIX_FINISH;
591 v.badtree := '1';
592 else
593 v.state := RADIX_LOOKUP;
594 """
595 # note that SelectableInt does big-endian! so the indices
596 # below *directly* match the spec, unlike microwatt which
597 # has to turn them around (to LE)
598 mbits = selectconcat(SelectableInt(0,1), mask_size)
599 mask = genmask(shift, 44)
600 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
601 log ("RADIX _segment_check nonzero", bin(nonzero.value))
602 log ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
603 if addr[0] != addr[1] or nonzero != 0:
604 return "segerror"
605 limit = shift + (31 - 12)
606 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
607 return "badtree"
608 new_shift = SelectableInt(limit.value - mbits.value, shift.bits)
609 # TODO verify that returned result is correct
610 return new_shift
611
612 def _check_perms(self, data, priv, mode):
613 """check page permissions
614 // Leaf PDE |
615 // |------------------------------| |----------------|
616 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
617 // |------------------------------| |----------------|
618 // [0] = V = Valid Bit |
619 // [1] = L = Leaf Bit = 1 if leaf |
620 // PDE |
621 // [2] = Sw = Sw bit 0. |
622 // [7:51] = RPN = Real Page Number, V
623 // real_page = RPN << 12 -------------> Logical OR
624 // [52:54] = Sw Bits 1:3 |
625 // [55] = R = Reference |
626 // [56] = C = Change V
627 // [58:59] = Att = Physical Address
628 // 0b00 = Normal Memory
629 // 0b01 = SAO
630 // 0b10 = Non Idenmpotent
631 // 0b11 = Tolerant I/O
632 // [60:63] = Encoded Access
633 // Authority
634 //
635 -- test leaf bit
636 -- check permissions and RC bits
637 perm_ok := '0';
638 if r.priv = '1' or data(3) = '0' then
639 if r.iside = '0' then
640 perm_ok := data(1) or (data(2) and not r.store);
641 else
642 -- no IAMR, so no KUEP support for now
643 -- deny execute permission if cache inhibited
644 perm_ok := data(0) and not data(5);
645 end if;
646 end if;
647 rc_ok := data(8) and (data(7) or not r.store);
648 if perm_ok = '1' and rc_ok = '1' then
649 v.state := RADIX_LOAD_TLB;
650 else
651 v.state := RADIX_FINISH;
652 v.perm_err := not perm_ok;
653 -- permission error takes precedence over RC error
654 v.rc_error := perm_ok;
655 end if;
656 """
657 # decode mode into something that matches microwatt equivalent code
658 instr_fetch, store = 0, 0
659 if mode == 'STORE':
660 store = 1
661 if mode == 'EXECUTE':
662 inst_fetch = 1
663
664 # check permissions and RC bits
665 perm_ok = 0
666 if priv == 1 or data[60] == 0:
667 if instr_fetch == 0:
668 perm_ok = data[62] | (data[61] & (store == 0))
669 # no IAMR, so no KUEP support for now
670 # deny execute permission if cache inhibited
671 perm_ok = data[63] & ~data[58]
672 rc_ok = data[55] & (data[56] | (store == 0))
673 if perm_ok == 1 and rc_ok == 1:
674 return True
675
676 return "perm_err" if perm_ok == 0 else "rc_err"
677
678 def _get_prtable_addr(self, shift, prtbl, addr, pid):
679 """
680 if r.addr(63) = '1' then
681 effpid := x"00000000";
682 else
683 effpid := r.pid;
684 end if;
685 x"00" & r.prtbl(55 downto 36) &
686 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
687 (effpid(31 downto 8) and finalmask(23 downto 0))) &
688 effpid(7 downto 0) & "0000";
689 """
690 finalmask = genmask(shift, 44)
691 finalmask24 = finalmask[20:44]
692 log ("_get_prtable_addr", shift, prtbl, addr, pid,
693 bin(finalmask24.value))
694 if addr[0].value == 1:
695 effpid = SelectableInt(0, 32)
696 else:
697 effpid = pid #self.pid # TODO, check on this
698 zero8 = SelectableInt(0, 8)
699 zero4 = SelectableInt(0, 4)
700 res = selectconcat(zero8,
701 prtbl[8:28], #
702 (prtbl[28:52] & ~finalmask24) | #
703 (effpid[0:24] & finalmask24), #
704 effpid[24:32],
705 zero4
706 )
707 return res
708
709 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
710 """
711 x"00" & r.pgbase(55 downto 19) &
712 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
713 "000";
714 """
715 log("pgbase",pgbase)
716 assert(pgbase.bits==56)
717 mask16 = genmask(mask_size+5, 16)
718 zero8 = SelectableInt(0, 8)
719 zero3 = SelectableInt(0, 3)
720 res = selectconcat(zero8,
721 pgbase[0:37],
722 (pgbase[37:53] & ~mask16) |
723 (addrsh & mask16),
724 zero3
725 )
726 return res
727
728 def _get_pte(self, shift, addr, pde):
729 """
730 x"00" &
731 ((r.pde(55 downto 12) and not finalmask) or
732 (r.addr(55 downto 12) and finalmask))
733 & r.pde(11 downto 0);
734 """
735 shift.value = 12
736 finalmask = genmask(shift, 44)
737 zero8 = SelectableInt(0, 8)
738 rpn = pde[8:52] # RPN = Real Page Number
739 abits = addr[8:52] # non-masked address bits
740 log(" get_pte RPN", hex(rpn.value))
741 log(" abits", hex(abits.value))
742 log(" shift", shift.value)
743 log(" finalmask", bin(finalmask.value))
744 res = selectconcat(zero8,
745 (rpn & ~finalmask) | #
746 (abits & finalmask), #
747 addr[52:64],
748 )
749 return res
750
751
752 class TestRadixMMU(unittest.TestCase):
753
754 def test_genmask(self):
755 shift = SelectableInt(5, 6)
756 mask = genmask(shift, 43)
757 log (" mask", bin(mask.value))
758
759 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
760
761 def test_RPDB(self):
762 inp = SelectableInt(0x40000000000300ad, 64)
763
764 rtdb = RPDB(inp)
765 log("rtdb",rtdb,bin(rtdb.value))
766 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
767
768 result = selectconcat(rtdb,SelectableInt(0,8))
769 log("result",result)
770
771 def test_get_pgtable_addr(self):
772
773 mem = None
774 caller = None
775 dut = RADIX(mem, caller)
776
777 mask_size=4
778 pgbase = SelectableInt(0,56)
779 addrsh = SelectableInt(0,16)
780 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
781 log("ret=", ret)
782 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
783
784 def test_walk_tree_1(self):
785
786 # test address as in
787 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
788 testaddr = 0x1000
789 expected = 0x1000
790
791 # starting prtbl
792 prtbl = 0x1000000
793
794 # set up dummy minimal ISACaller
795 spr = {'DSISR': SelectableInt(0, 64),
796 'DAR': SelectableInt(0, 64),
797 'PIDR': SelectableInt(0, 64),
798 'PRTBL': SelectableInt(prtbl, 64)
799 }
800 # set problem state == 0 (other unit tests, set to 1)
801 msr = SelectableInt(0, 64)
802 msr[MSRb.PR] = 0
803 class ISACaller: pass
804 caller = ISACaller()
805 caller.spr = spr
806 caller.msr = msr
807
808 shift = SelectableInt(5, 6)
809 mask = genmask(shift, 43)
810 log (" mask", bin(mask.value))
811
812 mem = Mem(row_bytes=8, initial_mem=testmem)
813 mem = RADIX(mem, caller)
814 # -----------------------------------------------
815 # |/|RTS1|/| RPDB | RTS2 | RPDS |
816 # -----------------------------------------------
817 # |0|1 2|3|4 55|56 58|59 63|
818 data = SelectableInt(0, 64)
819 data[1:3] = 0b01
820 data[56:59] = 0b11
821 data[59:64] = 0b01101 # mask
822 data[55] = 1
823 (rts, mbits, pgbase) = mem._decode_prte(data)
824 log (" rts", bin(rts.value), rts.bits)
825 log (" mbits", bin(mbits.value), mbits.bits)
826 log (" pgbase", hex(pgbase.value), pgbase.bits)
827 addr = SelectableInt(0x1000, 64)
828 check = mem._segment_check(addr, mbits, shift)
829 log (" segment check", check)
830
831 log("walking tree")
832 addr = SelectableInt(testaddr,64)
833 # pgbase = None
834 mode = None
835 #mbits = None
836 shift = rts
837 result = mem._walk_tree(addr, mode)
838 log(" walking tree result", result)
839 log("should be", testresult)
840 self.assertEqual(result.value, expected,
841 "expected 0x%x got 0x%x" % (expected,
842 result.value))
843
844 def test_walk_tree_2(self):
845
846 # test address slightly different
847 testaddr = 0x1101
848 expected = 0x5001101
849
850 # starting prtbl
851 prtbl = 0x1000000
852
853 # set up dummy minimal ISACaller
854 spr = {'DSISR': SelectableInt(0, 64),
855 'DAR': SelectableInt(0, 64),
856 'PIDR': SelectableInt(0, 64),
857 'PRTBL': SelectableInt(prtbl, 64)
858 }
859 # set problem state == 0 (other unit tests, set to 1)
860 msr = SelectableInt(0, 64)
861 msr[MSRb.PR] = 0
862 class ISACaller: pass
863 caller = ISACaller()
864 caller.spr = spr
865 caller.msr = msr
866
867 shift = SelectableInt(5, 6)
868 mask = genmask(shift, 43)
869 log (" mask", bin(mask.value))
870
871 mem = Mem(row_bytes=8, initial_mem=testmem2)
872 mem = RADIX(mem, caller)
873 # -----------------------------------------------
874 # |/|RTS1|/| RPDB | RTS2 | RPDS |
875 # -----------------------------------------------
876 # |0|1 2|3|4 55|56 58|59 63|
877 data = SelectableInt(0, 64)
878 data[1:3] = 0b01
879 data[56:59] = 0b11
880 data[59:64] = 0b01101 # mask
881 data[55] = 1
882 (rts, mbits, pgbase) = mem._decode_prte(data)
883 log (" rts", bin(rts.value), rts.bits)
884 log (" mbits", bin(mbits.value), mbits.bits)
885 log (" pgbase", hex(pgbase.value), pgbase.bits)
886 addr = SelectableInt(0x1000, 64)
887 check = mem._segment_check(addr, mbits, shift)
888 log (" segment check", check)
889
890 log("walking tree")
891 addr = SelectableInt(testaddr,64)
892 # pgbase = None
893 mode = None
894 #mbits = None
895 shift = rts
896 result = mem._walk_tree(addr, mode)
897 log(" walking tree result", result)
898 log("should be", testresult)
899 self.assertEqual(result.value, expected,
900 "expected 0x%x got 0x%x" % (expected,
901 result.value))
902
903
904 if __name__ == '__main__':
905 unittest.main()