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pass the mode (LOAD,EXECUTE,STORE) through ISACaller RADIX MMU
[openpower-isa.git] / src / openpower / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 #from nmigen.back.pysim import Settle
17 from copy import copy
18 from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from openpower.decoder.helpers import exts, gtu, ltu, undefined
21 from openpower.decoder.isa.mem import Mem, MemException
22 from openpower.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 print("addrshift")
52 print(addr)
53 print(shift)
54 x = addr.value >> shift.value
55 return SelectableInt(x, 16)
56
57 def RTS2(data):
58 return data[56:59]
59
60 def RTS1(data):
61 return data[1:3]
62
63 def RTS(data):
64 zero = SelectableInt(0, 1)
65 return selectconcat(zero, RTS2(data), RTS1(data))
66
67 def NLB(x):
68 """
69 Next Level Base
70 right shifted by 8
71 """
72 return x[4:56] # python numbering end+1
73
74 def NLS(x):
75 """
76 Next Level Size (PATS and RPDS in same bits btw)
77 NLS >= 5
78 """
79 return x[59:64] # python numbering end+1
80
81 def RPDB(x):
82 """
83 Root Page Directory Base
84 power isa docs says 4:55 investigate
85 """
86 return x[8:56] # python numbering end+1
87
88 """
89 Get Root Page
90
91 //Accessing 2nd double word of partition table (pate1)
92 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
93 // PTCR Layout
94 // ====================================================
95 // -----------------------------------------------
96 // | /// | PATB | /// | PATS |
97 // -----------------------------------------------
98 // 0 4 51 52 58 59 63
99 // PATB[4:51] holds the base address of the Partition Table,
100 // right shifted by 12 bits.
101 // This is because the address of the Partition base is
102 // 4k aligned. Hence, the lower 12bits, which are always
103 // 0 are ommitted from the PTCR.
104 //
105 // Thus, The Partition Table Base is obtained by (PATB << 12)
106 //
107 // PATS represents the partition table size right-shifted by 12 bits.
108 // The minimal size of the partition table is 4k.
109 // Thus partition table size = (1 << PATS + 12).
110 //
111 // Partition Table
112 // ====================================================
113 // 0 PATE0 63 PATE1 127
114 // |----------------------|----------------------|
115 // | | |
116 // |----------------------|----------------------|
117 // | | |
118 // |----------------------|----------------------|
119 // | | | <-- effLPID
120 // |----------------------|----------------------|
121 // .
122 // .
123 // .
124 // |----------------------|----------------------|
125 // | | |
126 // |----------------------|----------------------|
127 //
128 // The effective LPID forms the index into the Partition Table.
129 //
130 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
131 // corresponding to that partition.
132 //
133 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
134 //
135 // PATE0 Layout
136 // -----------------------------------------------
137 // |1|RTS1|/| RPDB | RTS2 | RPDS |
138 // -----------------------------------------------
139 // 0 1 2 3 4 55 56 58 59 63
140 //
141 // HR[0] : For Radix Page table, first bit should be 1.
142 // RTS1[1:2] : Gives one fragment of the Radix treesize
143 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
144 // RTS = (RTS1 << 3 + RTS2) + 31.
145 //
146 // RPDB[4:55] = Root Page Directory Base.
147 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
148 // Thus, Root page directory size = 1 << (RPDS + 3).
149 // Note: RPDS >= 5.
150 //
151 // PATE1 Layout
152 // -----------------------------------------------
153 // |///| PRTB | // | PRTS |
154 // -----------------------------------------------
155 // 0 3 4 51 52 58 59 63
156 //
157 // PRTB[4:51] = Process Table Base. This is aligned to size.
158 // PRTS[59: 63] = Process Table Size right shifted by 12.
159 // Minimal size of the process table is 4k.
160 // Process Table Size = (1 << PRTS + 12).
161 // Note: PRTS <= 24.
162 //
163 // Computing the size aligned Process Table Base:
164 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
165 // Thus, the lower 12+PRTS bits of table_base will
166 // be zero.
167
168
169 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
170 //
171 // Process Table
172 // ==========================
173 // 0 PRTE0 63 PRTE1 127
174 // |----------------------|----------------------|
175 // | | |
176 // |----------------------|----------------------|
177 // | | |
178 // |----------------------|----------------------|
179 // | | | <-- effPID
180 // |----------------------|----------------------|
181 // .
182 // .
183 // .
184 // |----------------------|----------------------|
185 // | | |
186 // |----------------------|----------------------|
187 //
188 // The effective Process id (PID) forms the index into the Process Table.
189 //
190 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
191 // corresponding to that process
192 //
193 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
194 //
195 // PRTE0 Layout
196 // -----------------------------------------------
197 // |/|RTS1|/| RPDB | RTS2 | RPDS |
198 // -----------------------------------------------
199 // 0 1 2 3 4 55 56 58 59 63
200 //
201 // RTS1[1:2] : Gives one fragment of the Radix treesize
202 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
203 // RTS = (RTS1 << 3 + RTS2) << 31,
204 // since minimal Radix Tree size is 4G.
205 //
206 // RPDB = Root Page Directory Base.
207 // RPDS = Root Page Directory Size right shifted by 3.
208 // Thus, Root page directory size = RPDS << 3.
209 // Note: RPDS >= 5.
210 //
211 // PRTE1 Layout
212 // -----------------------------------------------
213 // | /// |
214 // -----------------------------------------------
215 // 0 63
216 // All bits are reserved.
217
218
219 """
220
221 testmem = {
222
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
225 0x800000000100000b,
226
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
229 0x8000000000040009,
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0
232 # R = 1 C = 1 ATT = 0 EAA 0x7
233 0xc000000000000187,
234
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
237 0x40000000000300ad,
238 }
239
240 # this one has a 2nd level RADIX with a RPN of 0x5000
241 testmem2 = {
242
243 0x10000: # PARTITION_TABLE_2 (not implemented yet)
244 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
245 0x800000000100000b,
246
247 0x30000: # RADIX_ROOT_PTE
248 # V = 1 L = 0 NLB = 0x400 NLS = 9
249 0x8000000000040009,
250 0x40000: # RADIX_SECOND_LEVEL
251 # V = 1 L = 1 SW = 0 RPN = 0x5000
252 # R = 1 C = 1 ATT = 0 EAA 0x7
253 0xc000000005000187,
254
255 0x1000000: # PROCESS_TABLE_3
256 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
257 0x40000000000300ad,
258 }
259
260 testresult = """
261 prtbl = 1000000
262 DCACHE GET 1000000 PROCESS_TABLE_3
263 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
264 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
265 DCACHE GET 10000 PARTITION_TABLE_2
266 translated done 1 err 0 badtree 0 addr 40000 pte 0
267 """
268
269 # see qemu/target/ppc/mmu-radix64.c for reference
270 class RADIX:
271 def __init__(self, mem, caller):
272 self.mem = mem
273 self.caller = caller
274 if caller is not None:
275 print("caller")
276 print(caller)
277 self.dsisr = self.caller.spr["DSISR"]
278 self.dar = self.caller.spr["DAR"]
279 self.pidr = self.caller.spr["PIDR"]
280 self.prtbl = self.caller.spr["PRTBL"]
281 self.msr = self.caller.msr
282
283 # cached page table stuff
284 self.pgtbl0 = 0
285 self.pt0_valid = False
286 self.pgtbl3 = 0
287 self.pt3_valid = False
288
289 def __call__(self, addr, sz):
290 val = self.ld(addr.value, sz, swap=False)
291 print("RADIX memread", addr, sz, val)
292 return SelectableInt(val, sz*8)
293
294 def ld(self, address, width=8, swap=True, check_in_mem=False,
295 instr_fetch=False):
296 if instr_fetch:
297 mode = 'EXECUTE'
298 else:
299 mode = 'LOAD'
300 print("RADIX: ld from addr 0x%x width %d mode %s" % \
301 (address, width, mode))
302
303 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
304 addr = SelectableInt(address, 64)
305 pte = self._walk_tree(addr, mode, priv)
306
307 if type(pte)==str:
308 print("error on load",pte)
309 return 0
310
311 # use pte to load from phys address
312 data = self.mem.ld(pte.value, width, swap, check_in_mem)
313 self.last_ld_addr = self.mem.last_ld_addr
314
315 # XXX set SPRs on error
316 return data
317
318 # TODO implement
319 def st(self, address, v, width=8, swap=True):
320 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
321
322 priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
323 mode = 'STORE'
324 addr = SelectableInt(address, 64)
325 pte = self._walk_tree(addr, mode, priv)
326
327 # use pte to store at phys address
328 res = self.mem.st(pte.value, v, width, swap)
329 self.last_st_addr = self.mem.last_st_addr
330
331 # XXX set SPRs on error
332 return res
333
334 def memassign(self, addr, sz, val):
335 print("memassign", addr, sz, val)
336 self.st(addr.value, val.value, sz, swap=False)
337
338 def _next_level(self, addr, check_in_mem):
339 # implement read access to mmu mem here
340
341 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
342 value = self.mem.ld(addr.value, 8, False, check_in_mem)
343 if value is None:
344 return "address lookup %x not found" % addr.value
345 # assert(value is not None, "address lookup %x not found" % addr.value)
346
347 data = SelectableInt(value, 64) # convert to SelectableInt
348 print("addr", hex(addr.value))
349 print("value", hex(value))
350 return data;
351
352 def _walk_tree(self, addr, mode, priv=1):
353 """walk tree
354
355 // vaddr 64 Bit
356 // vaddr |-----------------------------------------------------|
357 // | Unused | Used |
358 // |-----------|-----------------------------------------|
359 // | 0000000 | usefulBits = X bits (typically 52) |
360 // |-----------|-----------------------------------------|
361 // | |<--Cursize---->| |
362 // | | Index | |
363 // | | into Page | |
364 // | | Directory | |
365 // |-----------------------------------------------------|
366 // | |
367 // V |
368 // PDE |---------------------------| |
369 // |V|L|//| NLB |///|NLS| |
370 // |---------------------------| |
371 // PDE = Page Directory Entry |
372 // [0] = V = Valid Bit |
373 // [1] = L = Leaf bit. If 0, then |
374 // [4:55] = NLB = Next Level Base |
375 // right shifted by 8 |
376 // [59:63] = NLS = Next Level Size |
377 // | NLS >= 5 |
378 // | V
379 // | |--------------------------|
380 // | | usfulBits = X-Cursize |
381 // | |--------------------------|
382 // |---------------------><--NLS-->| |
383 // | Index | |
384 // | into | |
385 // | PDE | |
386 // |--------------------------|
387 // |
388 // If the next PDE obtained by |
389 // (NLB << 8 + 8 * index) is a |
390 // nonleaf, then repeat the above. |
391 // |
392 // If the next PDE is a leaf, |
393 // then Leaf PDE structure is as |
394 // follows |
395 // |
396 // |
397 // Leaf PDE |
398 // |------------------------------| |----------------|
399 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
400 // |------------------------------| |----------------|
401 // [0] = V = Valid Bit |
402 // [1] = L = Leaf Bit = 1 if leaf |
403 // PDE |
404 // [2] = Sw = Sw bit 0. |
405 // [7:51] = RPN = Real Page Number, V
406 // real_page = RPN << 12 -------------> Logical OR
407 // [52:54] = Sw Bits 1:3 |
408 // [55] = R = Reference |
409 // [56] = C = Change V
410 // [58:59] = Att = Physical Address
411 // 0b00 = Normal Memory
412 // 0b01 = SAO
413 // 0b10 = Non Idenmpotent
414 // 0b11 = Tolerant I/O
415 // [60:63] = Encoded Access
416 // Authority
417 //
418 """
419 # get sprs
420 print("_walk_tree")
421 pidr = self.caller.spr["PIDR"]
422 prtbl = self.caller.spr["PRTBL"]
423 print("PIDR", pidr)
424 print("PRTBL", prtbl)
425 p = addr[55:63]
426 print("last 8 bits ----------")
427 print
428
429 # get address of root entry
430 # need to fetch process table entry
431 # v.shift := unsigned('0' & r.prtbl(4 downto 0));
432 shift = selectconcat(SelectableInt(0, 1), NLS(prtbl))
433 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
434 print("starting with prtable, addr_next", addr_next)
435
436 assert(addr_next.bits == 64)
437 #only for first unit tests assert(addr_next.value == 0x1000000)
438
439 # read an entry from prtable, decode PTRE
440 data = self._next_level(addr_next, check_in_mem=False)
441 print("pr_table", data)
442 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
443 (rts, mbits, pgbase) = self._decode_prte(pgtbl)
444 print("pgbase", pgbase)
445
446 # WIP
447 if mbits == 0:
448 exc = MemException("invalid")
449 exc.mode = mode
450 raise exc
451
452 # mask_size := mbits(4 downto 0);
453 mask_size = mbits[0:5]
454 assert(mask_size.bits == 5)
455 print("before segment check ==========")
456 print("mask_size:", bin(mask_size.value))
457 print("mbits:", bin(mbits.value))
458
459 print("calling segment_check")
460
461 shift = self._segment_check(addr, mask_size, shift)
462 print("shift", shift)
463
464 if isinstance(addr, str):
465 return addr
466 if isinstance(shift, str):
467 return shift
468
469 old_shift = shift
470
471 mask = mask_size
472
473 # walk tree
474 while True:
475 addrsh = addrshift(addr, shift)
476 print("addrsh",addrsh)
477
478 print("calling _get_pgtable_addr")
479 print(mask) #SelectableInt(value=0x9, bits=4)
480 print(pgbase) #SelectableInt(value=0x40000, bits=56)
481 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
482 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
483 print("DONE addr_next", addr_next)
484
485 print("nextlevel----------------------------")
486 # read an entry
487 data = self._next_level(addr_next, check_in_mem=False)
488 valid = rpte_valid(data)
489 leaf = rpte_leaf(data)
490
491 print(" valid, leaf", valid, leaf)
492 if not valid:
493 exc = MemException("invalid")
494 exc.mode = mode
495 raise exc
496 if leaf:
497 print ("is leaf, checking perms")
498 ok = self._check_perms(data, priv, mode)
499 if ok == True: # data was ok, found phys address, return it?
500 paddr = self._get_pte(addrsh, addr, data)
501 print (" phys addr", hex(paddr.value))
502 return paddr
503 return ok # return the error code
504 else:
505 newlookup = self._new_lookup(data, shift, old_shift)
506 if isinstance(newlookup, str):
507 return newlookup
508 old_shift = shift # store old_shift before updating shift
509 shift, mask, pgbase = newlookup
510 print (" next level", shift, mask, pgbase)
511
512 def _get_pgbase(self, data):
513 """
514 v.pgbase := data(55 downto 8) & x"00"; NLB?
515 """
516 zero8 = SelectableInt(0, 8)
517 ret = selectconcat(data[8:56], zero8)
518 assert(ret.bits==56)
519 return ret
520
521 def _new_lookup(self, data, shift, old_shift):
522 """
523 mbits := unsigned('0' & data(4 downto 0));
524 if mbits < 5 or mbits > 16 or mbits > r.shift then
525 v.state := RADIX_FINISH;
526 v.badtree := '1'; -- throw error
527 else
528 v.shift := v.shift - mbits;
529 v.mask_size := mbits(4 downto 0);
530 v.pgbase := data(55 downto 8) & x"00"; NLB?
531 v.state := RADIX_LOOKUP; --> next level
532 end if;
533 """
534 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
535 print("mbits=", mbits)
536 if mbits < 5 or mbits > 16 or mbits > old_shift:
537 print("badtree")
538 return "badtree"
539 # reduce shift (has to be done at same bitwidth)
540 shift = shift - mbits
541 assert mbits.bits == 6
542 mask_size = mbits[2:6] # get 4 LSBs from 6-bit (using MSB0 numbering)
543 pgbase = self._get_pgbase(data)
544 return shift, mask_size, pgbase
545
546 def _decode_prte(self, data):
547 """PRTE0 Layout
548 -----------------------------------------------
549 |/|RTS1|/| RPDB | RTS2 | RPDS |
550 -----------------------------------------------
551 0 1 2 3 4 55 56 58 59 63
552 """
553 # note that SelectableInt does big-endian! so the indices
554 # below *directly* match the spec, unlike microwatt which
555 # has to turn them around (to LE)
556 rts, mbits = self._get_rts_nls(data)
557 pgbase = self._get_pgbase(data)
558
559 return (rts, mbits, pgbase)
560
561 def _get_rts_nls(self, data):
562 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
563 # RTS1 RTS2
564 rts = RTS(data)
565 assert(rts.bits == 6) # variable rts : unsigned(5 downto 0);
566 print("shift", rts)
567
568 # mbits := unsigned('0' & data(4 downto 0));
569 mbits = selectconcat(SelectableInt(0, 1), NLS(data))
570 assert(mbits.bits == 6) #variable mbits : unsigned(5 downto 0);
571
572 return rts, mbits
573
574 def _segment_check(self, addr, mask_size, shift):
575 """checks segment valid
576 mbits := '0' & r.mask_size;
577 v.shift := r.shift + (31 - 12) - mbits;
578 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
579 if r.addr(63) /= r.addr(62) or nonzero = '1' then
580 v.state := RADIX_FINISH;
581 v.segerror := '1';
582 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
583 v.state := RADIX_FINISH;
584 v.badtree := '1';
585 else
586 v.state := RADIX_LOOKUP;
587 """
588 # note that SelectableInt does big-endian! so the indices
589 # below *directly* match the spec, unlike microwatt which
590 # has to turn them around (to LE)
591 mbits = selectconcat(SelectableInt(0,1), mask_size)
592 mask = genmask(shift, 44)
593 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
594 print ("RADIX _segment_check nonzero", bin(nonzero.value))
595 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
596 if addr[0] != addr[1] or nonzero != 0:
597 return "segerror"
598 limit = shift + (31 - 12)
599 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
600 return "badtree"
601 new_shift = SelectableInt(limit.value - mbits.value, shift.bits)
602 # TODO verify that returned result is correct
603 return new_shift
604
605 def _check_perms(self, data, priv, mode):
606 """check page permissions
607 // Leaf PDE |
608 // |------------------------------| |----------------|
609 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
610 // |------------------------------| |----------------|
611 // [0] = V = Valid Bit |
612 // [1] = L = Leaf Bit = 1 if leaf |
613 // PDE |
614 // [2] = Sw = Sw bit 0. |
615 // [7:51] = RPN = Real Page Number, V
616 // real_page = RPN << 12 -------------> Logical OR
617 // [52:54] = Sw Bits 1:3 |
618 // [55] = R = Reference |
619 // [56] = C = Change V
620 // [58:59] = Att = Physical Address
621 // 0b00 = Normal Memory
622 // 0b01 = SAO
623 // 0b10 = Non Idenmpotent
624 // 0b11 = Tolerant I/O
625 // [60:63] = Encoded Access
626 // Authority
627 //
628 -- test leaf bit
629 -- check permissions and RC bits
630 perm_ok := '0';
631 if r.priv = '1' or data(3) = '0' then
632 if r.iside = '0' then
633 perm_ok := data(1) or (data(2) and not r.store);
634 else
635 -- no IAMR, so no KUEP support for now
636 -- deny execute permission if cache inhibited
637 perm_ok := data(0) and not data(5);
638 end if;
639 end if;
640 rc_ok := data(8) and (data(7) or not r.store);
641 if perm_ok = '1' and rc_ok = '1' then
642 v.state := RADIX_LOAD_TLB;
643 else
644 v.state := RADIX_FINISH;
645 v.perm_err := not perm_ok;
646 -- permission error takes precedence over RC error
647 v.rc_error := perm_ok;
648 end if;
649 """
650 # decode mode into something that matches microwatt equivalent code
651 instr_fetch, store = 0, 0
652 if mode == 'STORE':
653 store = 1
654 if mode == 'EXECUTE':
655 inst_fetch = 1
656
657 # check permissions and RC bits
658 perm_ok = 0
659 if priv == 1 or data[60] == 0:
660 if instr_fetch == 0:
661 perm_ok = data[62] | (data[61] & (store == 0))
662 # no IAMR, so no KUEP support for now
663 # deny execute permission if cache inhibited
664 perm_ok = data[63] & ~data[58]
665 rc_ok = data[55] & (data[56] | (store == 0))
666 if perm_ok == 1 and rc_ok == 1:
667 return True
668
669 return "perm_err" if perm_ok == 0 else "rc_err"
670
671 def _get_prtable_addr(self, shift, prtbl, addr, pid):
672 """
673 if r.addr(63) = '1' then
674 effpid := x"00000000";
675 else
676 effpid := r.pid;
677 end if;
678 x"00" & r.prtbl(55 downto 36) &
679 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
680 (effpid(31 downto 8) and finalmask(23 downto 0))) &
681 effpid(7 downto 0) & "0000";
682 """
683 finalmask = genmask(shift, 44)
684 finalmask24 = finalmask[20:44]
685 print ("_get_prtable_addr", shift, prtbl, addr, pid,
686 bin(finalmask24.value))
687 if addr[0].value == 1:
688 effpid = SelectableInt(0, 32)
689 else:
690 effpid = pid #self.pid # TODO, check on this
691 zero8 = SelectableInt(0, 8)
692 zero4 = SelectableInt(0, 4)
693 res = selectconcat(zero8,
694 prtbl[8:28], #
695 (prtbl[28:52] & ~finalmask24) | #
696 (effpid[0:24] & finalmask24), #
697 effpid[24:32],
698 zero4
699 )
700 return res
701
702 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
703 """
704 x"00" & r.pgbase(55 downto 19) &
705 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
706 "000";
707 """
708 print("pgbase",pgbase)
709 assert(pgbase.bits==56)
710 mask16 = genmask(mask_size+5, 16)
711 zero8 = SelectableInt(0, 8)
712 zero3 = SelectableInt(0, 3)
713 res = selectconcat(zero8,
714 pgbase[0:37],
715 (pgbase[37:53] & ~mask16) |
716 (addrsh & mask16),
717 zero3
718 )
719 return res
720
721 def _get_pte(self, shift, addr, pde):
722 """
723 x"00" &
724 ((r.pde(55 downto 12) and not finalmask) or
725 (r.addr(55 downto 12) and finalmask))
726 & r.pde(11 downto 0);
727 """
728 shift.value = 12
729 finalmask = genmask(shift, 44)
730 zero8 = SelectableInt(0, 8)
731 rpn = pde[8:52] # RPN = Real Page Number
732 abits = addr[8:52] # non-masked address bits
733 print(" get_pte RPN", hex(rpn.value))
734 print(" abits", hex(abits.value))
735 print(" shift", shift.value)
736 print(" finalmask", bin(finalmask.value))
737 res = selectconcat(zero8,
738 (rpn & ~finalmask) | #
739 (abits & finalmask), #
740 addr[52:64],
741 )
742 return res
743
744
745 class TestRadixMMU(unittest.TestCase):
746
747 def test_genmask(self):
748 shift = SelectableInt(5, 6)
749 mask = genmask(shift, 43)
750 print (" mask", bin(mask.value))
751
752 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
753
754 def test_RPDB(self):
755 inp = SelectableInt(0x40000000000300ad, 64)
756
757 rtdb = RPDB(inp)
758 print("rtdb",rtdb,bin(rtdb.value))
759 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
760
761 result = selectconcat(rtdb,SelectableInt(0,8))
762 print("result",result)
763
764 def test_get_pgtable_addr(self):
765
766 mem = None
767 caller = None
768 dut = RADIX(mem, caller)
769
770 mask_size=4
771 pgbase = SelectableInt(0,56)
772 addrsh = SelectableInt(0,16)
773 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
774 print("ret=", ret)
775 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
776
777 def test_walk_tree_1(self):
778
779 # test address as in
780 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
781 testaddr = 0x1000
782 expected = 0x1000
783
784 # starting prtbl
785 prtbl = 0x1000000
786
787 # set up dummy minimal ISACaller
788 spr = {'DSISR': SelectableInt(0, 64),
789 'DAR': SelectableInt(0, 64),
790 'PIDR': SelectableInt(0, 64),
791 'PRTBL': SelectableInt(prtbl, 64)
792 }
793 # set problem state == 0 (other unit tests, set to 1)
794 msr = SelectableInt(0, 64)
795 msr[MSRb.PR] = 0
796 class ISACaller: pass
797 caller = ISACaller()
798 caller.spr = spr
799 caller.msr = msr
800
801 shift = SelectableInt(5, 6)
802 mask = genmask(shift, 43)
803 print (" mask", bin(mask.value))
804
805 mem = Mem(row_bytes=8, initial_mem=testmem)
806 mem = RADIX(mem, caller)
807 # -----------------------------------------------
808 # |/|RTS1|/| RPDB | RTS2 | RPDS |
809 # -----------------------------------------------
810 # |0|1 2|3|4 55|56 58|59 63|
811 data = SelectableInt(0, 64)
812 data[1:3] = 0b01
813 data[56:59] = 0b11
814 data[59:64] = 0b01101 # mask
815 data[55] = 1
816 (rts, mbits, pgbase) = mem._decode_prte(data)
817 print (" rts", bin(rts.value), rts.bits)
818 print (" mbits", bin(mbits.value), mbits.bits)
819 print (" pgbase", hex(pgbase.value), pgbase.bits)
820 addr = SelectableInt(0x1000, 64)
821 check = mem._segment_check(addr, mbits, shift)
822 print (" segment check", check)
823
824 print("walking tree")
825 addr = SelectableInt(testaddr,64)
826 # pgbase = None
827 mode = None
828 #mbits = None
829 shift = rts
830 result = mem._walk_tree(addr, mode)
831 print(" walking tree result", result)
832 print("should be", testresult)
833 self.assertEqual(result.value, expected,
834 "expected 0x%x got 0x%x" % (expected,
835 result.value))
836
837 def test_walk_tree_2(self):
838
839 # test address slightly different
840 testaddr = 0x1101
841 expected = 0x5001101
842
843 # starting prtbl
844 prtbl = 0x1000000
845
846 # set up dummy minimal ISACaller
847 spr = {'DSISR': SelectableInt(0, 64),
848 'DAR': SelectableInt(0, 64),
849 'PIDR': SelectableInt(0, 64),
850 'PRTBL': SelectableInt(prtbl, 64)
851 }
852 # set problem state == 0 (other unit tests, set to 1)
853 msr = SelectableInt(0, 64)
854 msr[MSRb.PR] = 0
855 class ISACaller: pass
856 caller = ISACaller()
857 caller.spr = spr
858 caller.msr = msr
859
860 shift = SelectableInt(5, 6)
861 mask = genmask(shift, 43)
862 print (" mask", bin(mask.value))
863
864 mem = Mem(row_bytes=8, initial_mem=testmem2)
865 mem = RADIX(mem, caller)
866 # -----------------------------------------------
867 # |/|RTS1|/| RPDB | RTS2 | RPDS |
868 # -----------------------------------------------
869 # |0|1 2|3|4 55|56 58|59 63|
870 data = SelectableInt(0, 64)
871 data[1:3] = 0b01
872 data[56:59] = 0b11
873 data[59:64] = 0b01101 # mask
874 data[55] = 1
875 (rts, mbits, pgbase) = mem._decode_prte(data)
876 print (" rts", bin(rts.value), rts.bits)
877 print (" mbits", bin(mbits.value), mbits.bits)
878 print (" pgbase", hex(pgbase.value), pgbase.bits)
879 addr = SelectableInt(0x1000, 64)
880 check = mem._segment_check(addr, mbits, shift)
881 print (" segment check", check)
882
883 print("walking tree")
884 addr = SelectableInt(testaddr,64)
885 # pgbase = None
886 mode = None
887 #mbits = None
888 shift = rts
889 result = mem._walk_tree(addr, mode)
890 print(" walking tree result", result)
891 print("should be", testresult)
892 self.assertEqual(result.value, expected,
893 "expected 0x%x got 0x%x" % (expected,
894 result.value))
895
896
897 if __name__ == '__main__':
898 unittest.main()