1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
16 #from nmigen.back.pysim import Settle
18 from openpower
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
20 from openpower
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
21 from openpower
.decoder
.isa
.mem
import Mem
, MemException
22 from openpower
.consts
import MSRb
# big-endian (PowerISA versions)
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift
, size
):
30 res
= SelectableInt(0, size
)
33 res
[size
-1-i
] = SelectableInt(1, 1)
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr
,shift
):
54 x
= addr
.value
>> shift
.value
55 return SelectableInt(x
, 16)
64 zero
= SelectableInt(0, 1)
65 return selectconcat(zero
, RTS2(data
), RTS1(data
))
72 return x
[4:56] # python numbering end+1
76 Next Level Size (PATS and RPDS in same bits btw)
79 return x
[59:64] # python numbering end+1
83 Root Page Directory Base
84 power isa docs says 4:55 investigate
86 return x
[8:56] # python numbering end+1
91 //Accessing 2nd double word of partition table (pate1)
92 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
94 // ====================================================
95 // -----------------------------------------------
96 // | /// | PATB | /// | PATS |
97 // -----------------------------------------------
99 // PATB[4:51] holds the base address of the Partition Table,
100 // right shifted by 12 bits.
101 // This is because the address of the Partition base is
102 // 4k aligned. Hence, the lower 12bits, which are always
103 // 0 are ommitted from the PTCR.
105 // Thus, The Partition Table Base is obtained by (PATB << 12)
107 // PATS represents the partition table size right-shifted by 12 bits.
108 // The minimal size of the partition table is 4k.
109 // Thus partition table size = (1 << PATS + 12).
112 // ====================================================
113 // 0 PATE0 63 PATE1 127
114 // |----------------------|----------------------|
116 // |----------------------|----------------------|
118 // |----------------------|----------------------|
120 // |----------------------|----------------------|
124 // |----------------------|----------------------|
126 // |----------------------|----------------------|
128 // The effective LPID forms the index into the Partition Table.
130 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
131 // corresponding to that partition.
133 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
136 // -----------------------------------------------
137 // |1|RTS1|/| RPDB | RTS2 | RPDS |
138 // -----------------------------------------------
139 // 0 1 2 3 4 55 56 58 59 63
141 // HR[0] : For Radix Page table, first bit should be 1.
142 // RTS1[1:2] : Gives one fragment of the Radix treesize
143 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
144 // RTS = (RTS1 << 3 + RTS2) + 31.
146 // RPDB[4:55] = Root Page Directory Base.
147 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
148 // Thus, Root page directory size = 1 << (RPDS + 3).
152 // -----------------------------------------------
153 // |///| PRTB | // | PRTS |
154 // -----------------------------------------------
155 // 0 3 4 51 52 58 59 63
157 // PRTB[4:51] = Process Table Base. This is aligned to size.
158 // PRTS[59: 63] = Process Table Size right shifted by 12.
159 // Minimal size of the process table is 4k.
160 // Process Table Size = (1 << PRTS + 12).
163 // Computing the size aligned Process Table Base:
164 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
165 // Thus, the lower 12+PRTS bits of table_base will
169 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
172 // ==========================
173 // 0 PRTE0 63 PRTE1 127
174 // |----------------------|----------------------|
176 // |----------------------|----------------------|
178 // |----------------------|----------------------|
180 // |----------------------|----------------------|
184 // |----------------------|----------------------|
186 // |----------------------|----------------------|
188 // The effective Process id (PID) forms the index into the Process Table.
190 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
191 // corresponding to that process
193 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
196 // -----------------------------------------------
197 // |/|RTS1|/| RPDB | RTS2 | RPDS |
198 // -----------------------------------------------
199 // 0 1 2 3 4 55 56 58 59 63
201 // RTS1[1:2] : Gives one fragment of the Radix treesize
202 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
203 // RTS = (RTS1 << 3 + RTS2) << 31,
204 // since minimal Radix Tree size is 4G.
206 // RPDB = Root Page Directory Base.
207 // RPDS = Root Page Directory Size right shifted by 3.
208 // Thus, Root page directory size = RPDS << 3.
212 // -----------------------------------------------
214 // -----------------------------------------------
216 // All bits are reserved.
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0
232 # R = 1 C = 1 ATT = 0 EAA 0x7
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
240 # this one has a 2nd level RADIX with a RPN of 0x5000
243 0x10000: # PARTITION_TABLE_2 (not implemented yet)
244 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
247 0x30000: # RADIX_ROOT_PTE
248 # V = 1 L = 0 NLB = 0x400 NLS = 9
250 0x40000: # RADIX_SECOND_LEVEL
251 # V = 1 L = 1 SW = 0 RPN = 0x5000
252 # R = 1 C = 1 ATT = 0 EAA 0x7
255 0x1000000: # PROCESS_TABLE_3
256 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
262 DCACHE GET 1000000 PROCESS_TABLE_3
263 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
264 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
265 DCACHE GET 10000 PARTITION_TABLE_2
266 translated done 1 err 0 badtree 0 addr 40000 pte 0
269 # see qemu/target/ppc/mmu-radix64.c for reference
271 def __init__(self
, mem
, caller
):
274 if caller
is not None:
277 self
.dsisr
= self
.caller
.spr
["DSISR"]
278 self
.dar
= self
.caller
.spr
["DAR"]
279 self
.pidr
= self
.caller
.spr
["PIDR"]
280 self
.prtbl
= self
.caller
.spr
["PRTBL"]
281 self
.msr
= self
.caller
.msr
283 # cached page table stuff
285 self
.pt0_valid
= False
287 self
.pt3_valid
= False
289 def __call__(self
, addr
, sz
):
290 val
= self
.ld(addr
.value
, sz
, swap
=False)
291 print("RADIX memread", addr
, sz
, val
)
292 return SelectableInt(val
, sz
*8)
294 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False,
300 priv
= ~
(self
.msr
[MSRb
.PR
].value
) # problem-state ==> privileged
301 virt
= (self
.msr
[MSRb
.DR
].value
) # DR -> virtual
302 print("RADIX: ld from addr 0x%x width %d mode %s "
303 "priv %d virt %d" % (address
, width
, mode
, priv
, virt
))
305 # virtual mode does a lookup to new address, otherwise use real addr
306 addr
= SelectableInt(address
, 64)
308 addr
= self
._walk
_tree
(addr
, mode
, priv
)
311 # use address to load from phys address
312 data
= self
.mem
.ld(addr
, width
, swap
, check_in_mem
)
313 self
.last_ld_addr
= self
.mem
.last_ld_addr
315 # XXX set SPRs on error
319 def st(self
, address
, v
, width
=8, swap
=True):
321 priv
= ~
(self
.msr
[MSRb
.PR
].value
) # problem-state ==> privileged
322 virt
= (self
.msr
[MSRb
.DR
].value
) # DR -> virtual
323 print("RADIX: st to addr 0x%x width %d data %x "
324 "priv %d virt %d " % (address
, width
, v
, priv
, virt
))
327 # virtual mode does a lookup to new address, otherwise use real addr
328 addr
= SelectableInt(address
, 64)
330 addr
= self
._walk
_tree
(addr
, mode
, priv
)
333 # use address to store at phys address
334 res
= self
.mem
.st(addr
, v
, width
, swap
)
335 self
.last_st_addr
= self
.mem
.last_st_addr
337 # XXX set SPRs on error
340 def memassign(self
, addr
, sz
, val
):
341 print("memassign", addr
, sz
, val
)
342 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
344 def _next_level(self
, addr
, check_in_mem
):
345 # implement read access to mmu mem here
347 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
348 value
= self
.mem
.ld(addr
.value
, 8, False, check_in_mem
)
350 return "address lookup %x not found" % addr
.value
351 # assert(value is not None, "address lookup %x not found" % addr.value)
353 data
= SelectableInt(value
, 64) # convert to SelectableInt
354 print("addr", hex(addr
.value
))
355 print("value", hex(value
))
358 def _walk_tree(self
, addr
, mode
, priv
=1):
362 // vaddr |-----------------------------------------------------|
364 // |-----------|-----------------------------------------|
365 // | 0000000 | usefulBits = X bits (typically 52) |
366 // |-----------|-----------------------------------------|
367 // | |<--Cursize---->| |
371 // |-----------------------------------------------------|
374 // PDE |---------------------------| |
375 // |V|L|//| NLB |///|NLS| |
376 // |---------------------------| |
377 // PDE = Page Directory Entry |
378 // [0] = V = Valid Bit |
379 // [1] = L = Leaf bit. If 0, then |
380 // [4:55] = NLB = Next Level Base |
381 // right shifted by 8 |
382 // [59:63] = NLS = Next Level Size |
385 // | |--------------------------|
386 // | | usfulBits = X-Cursize |
387 // | |--------------------------|
388 // |---------------------><--NLS-->| |
392 // |--------------------------|
394 // If the next PDE obtained by |
395 // (NLB << 8 + 8 * index) is a |
396 // nonleaf, then repeat the above. |
398 // If the next PDE is a leaf, |
399 // then Leaf PDE structure is as |
404 // |------------------------------| |----------------|
405 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
406 // |------------------------------| |----------------|
407 // [0] = V = Valid Bit |
408 // [1] = L = Leaf Bit = 1 if leaf |
410 // [2] = Sw = Sw bit 0. |
411 // [7:51] = RPN = Real Page Number, V
412 // real_page = RPN << 12 -------------> Logical OR
413 // [52:54] = Sw Bits 1:3 |
414 // [55] = R = Reference |
415 // [56] = C = Change V
416 // [58:59] = Att = Physical Address
417 // 0b00 = Normal Memory
419 // 0b10 = Non Idenmpotent
420 // 0b11 = Tolerant I/O
421 // [60:63] = Encoded Access
427 pidr
= self
.caller
.spr
["PIDR"]
428 prtbl
= self
.caller
.spr
["PRTBL"]
430 print("PRTBL", prtbl
)
432 print("last 8 bits ----------")
435 # get address of root entry
436 # need to fetch process table entry
437 # v.shift := unsigned('0' & r.prtbl(4 downto 0));
438 shift
= selectconcat(SelectableInt(0, 1), NLS(prtbl
))
439 addr_next
= self
._get
_prtable
_addr
(shift
, prtbl
, addr
, pidr
)
440 print("starting with prtable, addr_next", addr_next
)
442 assert(addr_next
.bits
== 64)
443 #only for first unit tests assert(addr_next.value == 0x1000000)
445 # read an entry from prtable, decode PTRE
446 data
= self
._next
_level
(addr_next
, check_in_mem
=False)
447 print("pr_table", data
)
448 pgtbl
= data
# this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
449 (rts
, mbits
, pgbase
) = self
._decode
_prte
(pgtbl
)
450 print("pgbase", pgbase
)
454 exc
= MemException("invalid")
458 # mask_size := mbits(4 downto 0);
459 mask_size
= mbits
[0:5]
460 assert(mask_size
.bits
== 5)
461 print("before segment check ==========")
462 print("mask_size:", bin(mask_size
.value
))
463 print("mbits:", bin(mbits
.value
))
465 print("calling segment_check")
467 shift
= self
._segment
_check
(addr
, mask_size
, shift
)
468 print("shift", shift
)
470 if isinstance(addr
, str):
472 if isinstance(shift
, str):
481 addrsh
= addrshift(addr
, shift
)
482 print("addrsh",addrsh
)
484 print("calling _get_pgtable_addr")
485 print(mask
) #SelectableInt(value=0x9, bits=4)
486 print(pgbase
) #SelectableInt(value=0x40000, bits=56)
487 print(shift
) #SelectableInt(value=0x4, bits=16) #FIXME
488 addr_next
= self
._get
_pgtable
_addr
(mask
, pgbase
, addrsh
)
489 print("DONE addr_next", addr_next
)
491 print("nextlevel----------------------------")
493 data
= self
._next
_level
(addr_next
, check_in_mem
=False)
494 valid
= rpte_valid(data
)
495 leaf
= rpte_leaf(data
)
497 print(" valid, leaf", valid
, leaf
)
499 exc
= MemException("invalid")
503 print ("is leaf, checking perms")
504 ok
= self
._check
_perms
(data
, priv
, mode
)
505 if ok
== True: # data was ok, found phys address, return it?
506 paddr
= self
._get
_pte
(addrsh
, addr
, data
)
507 print (" phys addr", hex(paddr
.value
))
509 return ok
# return the error code
511 newlookup
= self
._new
_lookup
(data
, shift
, old_shift
)
512 if isinstance(newlookup
, str):
514 old_shift
= shift
# store old_shift before updating shift
515 shift
, mask
, pgbase
= newlookup
516 print (" next level", shift
, mask
, pgbase
)
518 def _get_pgbase(self
, data
):
520 v.pgbase := data(55 downto 8) & x"00"; NLB?
522 zero8
= SelectableInt(0, 8)
523 ret
= selectconcat(data
[8:56], zero8
)
527 def _new_lookup(self
, data
, shift
, old_shift
):
529 mbits := unsigned('0' & data(4 downto 0));
530 if mbits < 5 or mbits > 16 or mbits > r.shift then
531 v.state := RADIX_FINISH;
532 v.badtree := '1'; -- throw error
534 v.shift := v.shift - mbits;
535 v.mask_size := mbits(4 downto 0);
536 v.pgbase := data(55 downto 8) & x"00"; NLB?
537 v.state := RADIX_LOOKUP; --> next level
540 mbits
= selectconcat(SelectableInt(0, 1), NLS(data
))
541 print("mbits=", mbits
)
542 if mbits
< 5 or mbits
> 16 or mbits
> old_shift
:
545 # reduce shift (has to be done at same bitwidth)
546 shift
= shift
- mbits
547 assert mbits
.bits
== 6
548 mask_size
= mbits
[2:6] # get 4 LSBs from 6-bit (using MSB0 numbering)
549 pgbase
= self
._get
_pgbase
(data
)
550 return shift
, mask_size
, pgbase
552 def _decode_prte(self
, data
):
554 -----------------------------------------------
555 |/|RTS1|/| RPDB | RTS2 | RPDS |
556 -----------------------------------------------
557 0 1 2 3 4 55 56 58 59 63
559 # note that SelectableInt does big-endian! so the indices
560 # below *directly* match the spec, unlike microwatt which
561 # has to turn them around (to LE)
562 rts
, mbits
= self
._get
_rts
_nls
(data
)
563 pgbase
= self
._get
_pgbase
(data
)
565 return (rts
, mbits
, pgbase
)
567 def _get_rts_nls(self
, data
):
568 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
571 assert(rts
.bits
== 6) # variable rts : unsigned(5 downto 0);
574 # mbits := unsigned('0' & data(4 downto 0));
575 mbits
= selectconcat(SelectableInt(0, 1), NLS(data
))
576 assert(mbits
.bits
== 6) #variable mbits : unsigned(5 downto 0);
580 def _segment_check(self
, addr
, mask_size
, shift
):
581 """checks segment valid
582 mbits := '0' & r.mask_size;
583 v.shift := r.shift + (31 - 12) - mbits;
584 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
585 if r.addr(63) /= r.addr(62) or nonzero = '1' then
586 v.state := RADIX_FINISH;
588 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
589 v.state := RADIX_FINISH;
592 v.state := RADIX_LOOKUP;
594 # note that SelectableInt does big-endian! so the indices
595 # below *directly* match the spec, unlike microwatt which
596 # has to turn them around (to LE)
597 mbits
= selectconcat(SelectableInt(0,1), mask_size
)
598 mask
= genmask(shift
, 44)
599 nonzero
= addr
[2:33] & mask
[13:44] # mask 31 LSBs (BE numbered 13:44)
600 print ("RADIX _segment_check nonzero", bin(nonzero
.value
))
601 print ("RADIX _segment_check addr[0-1]", addr
[0].value
, addr
[1].value
)
602 if addr
[0] != addr
[1] or nonzero
!= 0:
604 limit
= shift
+ (31 - 12)
605 if mbits
.value
< 5 or mbits
.value
> 16 or mbits
.value
> limit
.value
:
607 new_shift
= SelectableInt(limit
.value
- mbits
.value
, shift
.bits
)
608 # TODO verify that returned result is correct
611 def _check_perms(self
, data
, priv
, mode
):
612 """check page permissions
614 // |------------------------------| |----------------|
615 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
616 // |------------------------------| |----------------|
617 // [0] = V = Valid Bit |
618 // [1] = L = Leaf Bit = 1 if leaf |
620 // [2] = Sw = Sw bit 0. |
621 // [7:51] = RPN = Real Page Number, V
622 // real_page = RPN << 12 -------------> Logical OR
623 // [52:54] = Sw Bits 1:3 |
624 // [55] = R = Reference |
625 // [56] = C = Change V
626 // [58:59] = Att = Physical Address
627 // 0b00 = Normal Memory
629 // 0b10 = Non Idenmpotent
630 // 0b11 = Tolerant I/O
631 // [60:63] = Encoded Access
635 -- check permissions and RC bits
637 if r.priv = '1' or data(3) = '0' then
638 if r.iside = '0' then
639 perm_ok := data(1) or (data(2) and not r.store);
641 -- no IAMR, so no KUEP support for now
642 -- deny execute permission if cache inhibited
643 perm_ok := data(0) and not data(5);
646 rc_ok := data(8) and (data(7) or not r.store);
647 if perm_ok = '1' and rc_ok = '1' then
648 v.state := RADIX_LOAD_TLB;
650 v.state := RADIX_FINISH;
651 v.perm_err := not perm_ok;
652 -- permission error takes precedence over RC error
653 v.rc_error := perm_ok;
656 # decode mode into something that matches microwatt equivalent code
657 instr_fetch
, store
= 0, 0
660 if mode
== 'EXECUTE':
663 # check permissions and RC bits
665 if priv
== 1 or data
[60] == 0:
667 perm_ok
= data
[62] |
(data
[61] & (store
== 0))
668 # no IAMR, so no KUEP support for now
669 # deny execute permission if cache inhibited
670 perm_ok
= data
[63] & ~data
[58]
671 rc_ok
= data
[55] & (data
[56] |
(store
== 0))
672 if perm_ok
== 1 and rc_ok
== 1:
675 return "perm_err" if perm_ok
== 0 else "rc_err"
677 def _get_prtable_addr(self
, shift
, prtbl
, addr
, pid
):
679 if r.addr(63) = '1' then
680 effpid := x"00000000";
684 x"00" & r.prtbl(55 downto 36) &
685 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
686 (effpid(31 downto 8) and finalmask(23 downto 0))) &
687 effpid(7 downto 0) & "0000";
689 finalmask
= genmask(shift
, 44)
690 finalmask24
= finalmask
[20:44]
691 print ("_get_prtable_addr", shift
, prtbl
, addr
, pid
,
692 bin(finalmask24
.value
))
693 if addr
[0].value
== 1:
694 effpid
= SelectableInt(0, 32)
696 effpid
= pid
#self.pid # TODO, check on this
697 zero8
= SelectableInt(0, 8)
698 zero4
= SelectableInt(0, 4)
699 res
= selectconcat(zero8
,
701 (prtbl
[28:52] & ~finalmask24
) |
#
702 (effpid
[0:24] & finalmask24
), #
708 def _get_pgtable_addr(self
, mask_size
, pgbase
, addrsh
):
710 x"00" & r.pgbase(55 downto 19) &
711 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
714 print("pgbase",pgbase
)
715 assert(pgbase
.bits
==56)
716 mask16
= genmask(mask_size
+5, 16)
717 zero8
= SelectableInt(0, 8)
718 zero3
= SelectableInt(0, 3)
719 res
= selectconcat(zero8
,
721 (pgbase
[37:53] & ~mask16
) |
727 def _get_pte(self
, shift
, addr
, pde
):
730 ((r.pde(55 downto 12) and not finalmask) or
731 (r.addr(55 downto 12) and finalmask))
732 & r.pde(11 downto 0);
735 finalmask
= genmask(shift
, 44)
736 zero8
= SelectableInt(0, 8)
737 rpn
= pde
[8:52] # RPN = Real Page Number
738 abits
= addr
[8:52] # non-masked address bits
739 print(" get_pte RPN", hex(rpn
.value
))
740 print(" abits", hex(abits
.value
))
741 print(" shift", shift
.value
)
742 print(" finalmask", bin(finalmask
.value
))
743 res
= selectconcat(zero8
,
744 (rpn
& ~finalmask
) |
#
745 (abits
& finalmask
), #
751 class TestRadixMMU(unittest
.TestCase
):
753 def test_genmask(self
):
754 shift
= SelectableInt(5, 6)
755 mask
= genmask(shift
, 43)
756 print (" mask", bin(mask
.value
))
758 self
.assertEqual(mask
.value
, 0b11111, "mask should be 5 1s")
761 inp
= SelectableInt(0x40000000000300ad, 64)
764 print("rtdb",rtdb
,bin(rtdb
.value
))
765 self
.assertEqual(rtdb
.value
,0x300,"rtdb should be 0x300")
767 result
= selectconcat(rtdb
,SelectableInt(0,8))
768 print("result",result
)
770 def test_get_pgtable_addr(self
):
774 dut
= RADIX(mem
, caller
)
777 pgbase
= SelectableInt(0,56)
778 addrsh
= SelectableInt(0,16)
779 ret
= dut
._get
_pgtable
_addr
(mask_size
, pgbase
, addrsh
)
781 self
.assertEqual(ret
, 0, "pgtbl_addr should be 0")
783 def test_walk_tree_1(self
):
786 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
793 # set up dummy minimal ISACaller
794 spr
= {'DSISR': SelectableInt(0, 64),
795 'DAR': SelectableInt(0, 64),
796 'PIDR': SelectableInt(0, 64),
797 'PRTBL': SelectableInt(prtbl
, 64)
799 # set problem state == 0 (other unit tests, set to 1)
800 msr
= SelectableInt(0, 64)
802 class ISACaller
: pass
807 shift
= SelectableInt(5, 6)
808 mask
= genmask(shift
, 43)
809 print (" mask", bin(mask
.value
))
811 mem
= Mem(row_bytes
=8, initial_mem
=testmem
)
812 mem
= RADIX(mem
, caller
)
813 # -----------------------------------------------
814 # |/|RTS1|/| RPDB | RTS2 | RPDS |
815 # -----------------------------------------------
816 # |0|1 2|3|4 55|56 58|59 63|
817 data
= SelectableInt(0, 64)
820 data
[59:64] = 0b01101 # mask
822 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
823 print (" rts", bin(rts
.value
), rts
.bits
)
824 print (" mbits", bin(mbits
.value
), mbits
.bits
)
825 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
826 addr
= SelectableInt(0x1000, 64)
827 check
= mem
._segment
_check
(addr
, mbits
, shift
)
828 print (" segment check", check
)
830 print("walking tree")
831 addr
= SelectableInt(testaddr
,64)
836 result
= mem
._walk
_tree
(addr
, mode
)
837 print(" walking tree result", result
)
838 print("should be", testresult
)
839 self
.assertEqual(result
.value
, expected
,
840 "expected 0x%x got 0x%x" % (expected
,
843 def test_walk_tree_2(self
):
845 # test address slightly different
852 # set up dummy minimal ISACaller
853 spr
= {'DSISR': SelectableInt(0, 64),
854 'DAR': SelectableInt(0, 64),
855 'PIDR': SelectableInt(0, 64),
856 'PRTBL': SelectableInt(prtbl
, 64)
858 # set problem state == 0 (other unit tests, set to 1)
859 msr
= SelectableInt(0, 64)
861 class ISACaller
: pass
866 shift
= SelectableInt(5, 6)
867 mask
= genmask(shift
, 43)
868 print (" mask", bin(mask
.value
))
870 mem
= Mem(row_bytes
=8, initial_mem
=testmem2
)
871 mem
= RADIX(mem
, caller
)
872 # -----------------------------------------------
873 # |/|RTS1|/| RPDB | RTS2 | RPDS |
874 # -----------------------------------------------
875 # |0|1 2|3|4 55|56 58|59 63|
876 data
= SelectableInt(0, 64)
879 data
[59:64] = 0b01101 # mask
881 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
882 print (" rts", bin(rts
.value
), rts
.bits
)
883 print (" mbits", bin(mbits
.value
), mbits
.bits
)
884 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
885 addr
= SelectableInt(0x1000, 64)
886 check
= mem
._segment
_check
(addr
, mbits
, shift
)
887 print (" segment check", check
)
889 print("walking tree")
890 addr
= SelectableInt(testaddr
,64)
895 result
= mem
._walk
_tree
(addr
, mode
)
896 print(" walking tree result", result
)
897 print("should be", testresult
)
898 self
.assertEqual(result
.value
, expected
,
899 "expected 0x%x got 0x%x" % (expected
,
903 if __name__
== '__main__':