src/openpower/decoder/isa/test_caller_svindex.py

   1 """SVP64 unit test for doing strange things to SVSTATE, manually.
   2 """
   3 from nmigen import Module, Signal
   4 from nmigen.back.pysim import Simulator, Delay, Settle
   5 from nmutil.formaltest import FHDLTestCase
   6 import unittest
   7 from openpower.decoder.isa.caller import ISACaller
   8 from openpower.decoder.power_decoder import (create_pdecode)
   9 from openpower.decoder.power_decoder2 import (PowerDecode2)
  10 from openpower.simulator.program import Program
  11 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  12 from openpower.decoder.selectable_int import SelectableInt
  13 from openpower.decoder.orderedset import OrderedSet
  14 from openpower.decoder.isa.all import ISA
  15 from openpower.decoder.isa.test_caller import Register, run_tst
  16 from openpower.sv.trans.svp64 import SVP64Asm
  17 from openpower.consts import SVP64CROffs
  18 from copy import deepcopy
  19
  20
  21 class SVSTATETestCase(FHDLTestCase):
  22
  23     def _check_regs(self, sim, expected):
  24         print ("GPR")
  25         sim.gpr.dump()
  26         for i in range(32):
  27             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  28
  29     def test_sv_index(self):
  30         """sets VL=2 (via SVSTATE) with a manual srcstep/dststep,
  31             then does a scalar-result add.  the result should be:
  32
  33                 add 1, 6, 10
  34
  35             because whilst the Vector instruction was moved on by srcstep,
  36             the Scalar one is NOT moved on.
  37         """
  38         isa = SVP64Asm(['svindex 1, 31, 5, 0, 0, 0, 0'
  39                        ])
  40         lst = list(isa)
  41         print ("listing", lst)
  42
  43         # initial values in GPR regfile
  44         initial_regs = [0] * 32
  45         initial_regs[9] = 0x1234
  46         initial_regs[10] = 0x1111
  47         initial_regs[5] = 0x4321
  48         initial_regs[6] = 0x2223
  49
  50         # SVSTATE vl=10
  51         svstate = SVP64State()
  52         svstate.vl = 10 # VL
  53         svstate.maxvl = 10 # MAXVL
  54         print ("SVSTATE", bin(svstate.asint()))
  55
  56         # copy before running
  57         expected_regs = deepcopy(initial_regs)
  58         #expected_regs[1] = 0x3334
  59
  60         with Program(lst, bigendian=False) as program:
  61             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
  62             self._check_regs(sim, expected_regs)
  63
  64             print ("SVSTATE after", bin(sim.svstate.asint()))
  65             print ("        vl", bin(sim.svstate.vl))
  66             print ("        mvl", bin(sim.svstate.maxvl))
  67             print ("    srcstep", bin(sim.svstate.srcstep))
  68             print ("    dststep", bin(sim.svstate.dststep))
  69             print ("      RMpst", bin(sim.svstate.RMpst))
  70             print ("       SVme", bin(sim.svstate.SVme))
  71             print ("        mo0", bin(sim.svstate.mo0))
  72             print ("        mo1", bin(sim.svstate.mo1))
  73             print ("        mi0", bin(sim.svstate.mi0))
  74             print ("        mi1", bin(sim.svstate.mi1))
  75             print ("        mi2", bin(sim.svstate.mi2))
  76
  77     def run_tst_program(self, prog, initial_regs=None,
  78                               svstate=None):
  79         if initial_regs is None:
  80             initial_regs = [0] * 32
  81         simulator = run_tst(prog, initial_regs, svstate=svstate)
  82         simulator.gpr.dump()
  83         return simulator
  84
  85
  86 if __name__ == "__main__":
  87     unittest.main()
  88