src/openpower/decoder/isa/test_caller_svindex.py

   1 """SVP64 unit test for svindex
   2 svindex SVG,rmm,SVd,ew,yx,mm,sk
   3 """
   4 import unittest
   5 from copy import deepcopy
   6
   7 from nmutil.formaltest import FHDLTestCase
   8 from openpower.decoder.isa.caller import SVP64State, set_masked_reg
   9 from openpower.decoder.isa.test_caller import run_tst
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.simulator.program import Program
  12 from openpower.insndb.asm import SVP64Asm
  13
  14
  15 class SVSTATETestCase(FHDLTestCase):
  16
  17     def _check_regs(self, sim, expected):
  18         print("GPR")
  19         sim.gpr.dump()
  20         for i in range(32):
  21             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64),
  22                              "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i]))
  23
  24     def test_0_sv_index(self):
  25         """sets VL=10 (via SVSTATE) then does svindex mm=0, checks SPRs after
  26         """
  27         isa = SVP64Asm(['svindex 1, 15, 5, 0, 0, 0, 0'
  28                         ])
  29         lst = list(isa)
  30         print("listing", lst)
  31
  32         # initial values in GPR regfile
  33         initial_regs = [0] * 32
  34         initial_regs[9] = 0x1234
  35         initial_regs[10] = 0x1111
  36         initial_regs[5] = 0x4321
  37         initial_regs[6] = 0x2223
  38
  39         # SVSTATE vl=10
  40         svstate = SVP64State()
  41         svstate.vl = 10  # VL
  42         svstate.maxvl = 10  # MAXVL
  43         print("SVSTATE", bin(svstate.asint()))
  44
  45         # copy before running
  46         expected_regs = deepcopy(initial_regs)
  47         #expected_regs[1] = 0x3334
  48
  49         with Program(lst, bigendian=False) as program:
  50             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
  51             self._check_regs(sim, expected_regs)
  52
  53             print(sim.spr)
  54             SVSHAPE0 = sim.spr['SVSHAPE0']
  55             print("SVSTATE after", bin(sim.svstate.asint()))
  56             print("        vl", bin(sim.svstate.vl))
  57             print("        mvl", bin(sim.svstate.maxvl))
  58             print("    srcstep", bin(sim.svstate.srcstep))
  59             print("    dststep", bin(sim.svstate.dststep))
  60             print("      RMpst", bin(sim.svstate.RMpst))
  61             print("       SVme", bin(sim.svstate.SVme))
  62             print("        mo0", bin(sim.svstate.mo0))
  63             print("        mo1", bin(sim.svstate.mo1))
  64             print("        mi0", bin(sim.svstate.mi0))
  65             print("        mi1", bin(sim.svstate.mi1))
  66             print("        mi2", bin(sim.svstate.mi2))
  67             print("STATE0svgpr", hex(SVSHAPE0.svgpr))
  68             print("STATE0 xdim", SVSHAPE0.xdimsz)
  69             print("STATE0 ydim", SVSHAPE0.ydimsz)
  70             print("STATE0 skip", bin(SVSHAPE0.skip))
  71             print("STATE0  inv", SVSHAPE0.invxyz)
  72             print("STATE0order", SVSHAPE0.order)
  73             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
  74             self.assertEqual(sim.svstate.SVme, 0b01111)  # same as rmm
  75             # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
  76             self.assertEqual(sim.svstate.mi0, 0)
  77             self.assertEqual(sim.svstate.mi1, 1)
  78             self.assertEqual(sim.svstate.mi2, 2)
  79             self.assertEqual(sim.svstate.mo0, 3)
  80             self.assertEqual(sim.svstate.mo1, 0)
  81             for i in range(4):
  82                 shape = sim.spr['SVSHAPE%d' % i]
  83                 self.assertEqual(shape.svgpr, 2)  # SVG is shifted up by 1
  84
  85     def test_1_sv_index(self):
  86         """sets VL=10 (via SVSTATE) then does svindex mm=1, checks SPRs after
  87         """
  88         # rmm: bits 0-2 (MSB0) are 0b011 and bits 3-4 are 0b10.
  89         #      therefore rmm is 0b011 || 0b10 --> 0b01110 -> 14
  90         isa = SVP64Asm(['svindex 1, 14, 5, 0, 0, 1, 0'
  91                         ])
  92         lst = list(isa)
  93         print("listing", lst)
  94
  95         # initial values in GPR regfile
  96         initial_regs = [0] * 32
  97         initial_regs[9] = 0x1234
  98         initial_regs[10] = 0x1111
  99         initial_regs[5] = 0x4321
 100         initial_regs[6] = 0x2223
 101
 102         # SVSTATE vl=10
 103         svstate = SVP64State()
 104         svstate.vl = 10  # VL
 105         svstate.maxvl = 10  # MAXVL
 106         print("SVSTATE", bin(svstate.asint()))
 107
 108         # copy before running
 109         expected_regs = deepcopy(initial_regs)
 110         #expected_regs[1] = 0x3334
 111
 112         with Program(lst, bigendian=False) as program:
 113             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 114             self._check_regs(sim, expected_regs)
 115
 116             print(sim.spr)
 117             SVSHAPE2 = sim.spr['SVSHAPE2']
 118             print("SVSTATE after", bin(sim.svstate.asint()))
 119             print("        vl", bin(sim.svstate.vl))
 120             print("        mvl", bin(sim.svstate.maxvl))
 121             print("    srcstep", bin(sim.svstate.srcstep))
 122             print("    dststep", bin(sim.svstate.dststep))
 123             print("      RMpst", bin(sim.svstate.RMpst))
 124             print("       SVme", bin(sim.svstate.SVme))
 125             print("        mo0", bin(sim.svstate.mo0))
 126             print("        mo1", bin(sim.svstate.mo1))
 127             print("        mi0", bin(sim.svstate.mi0))
 128             print("        mi1", bin(sim.svstate.mi1))
 129             print("        mi2", bin(sim.svstate.mi2))
 130             print("STATE2svgpr", hex(SVSHAPE2.svgpr))
 131             print("STATE2 xdim", SVSHAPE2.xdimsz)
 132             print("STATE2 ydim", SVSHAPE2.ydimsz)
 133             print("STATE2 skip", bin(SVSHAPE2.skip))
 134             print("STATE2  inv", SVSHAPE2.invxyz)
 135             print("STATE2order", SVSHAPE2.order)
 136             self.assertEqual(sim.svstate.RMpst, 1)  # mm=1 so persist=1
 137             # rmm is 0b01110 which means mo0 = 2
 138             self.assertEqual(sim.svstate.mi0, 0)
 139             self.assertEqual(sim.svstate.mi1, 0)
 140             self.assertEqual(sim.svstate.mi2, 0)
 141             self.assertEqual(sim.svstate.mo0, 2)
 142             self.assertEqual(sim.svstate.mo1, 0)
 143             # and mo0 should be activated
 144             self.assertEqual(sim.svstate.SVme, 0b01000)
 145             # now check the SVSHAPEs. 2 was the one targetted
 146             self.assertEqual(SVSHAPE2.svgpr, 2)  # SVG is shifted up by 1
 147             self.assertEqual(SVSHAPE2.xdimsz, 5)  # SHAPE2 xdim set to 5
 148             self.assertEqual(SVSHAPE2.ydimsz, 1)  # SHAPE2 ydim 1
 149             # all others must be zero
 150             for i in [0, 1, 3]:
 151                 shape = sim.spr['SVSHAPE%d' % i]
 152                 self.assertEqual(shape.asint(), 0)  # all others zero
 153
 154     def test_0_sv_index_add(self):
 155         """sets VL=6 (via SVSTATE) then does svindex, and an add.
 156
 157         only RA is re-mapped via Indexing, not RB or RT
 158         """
 159         isa = SVP64Asm(['svindex 8, 1, 1, 0, 0, 0, 0',
 160                         'sv.add *8, *0, *0',
 161                         ])
 162         lst = list(isa)
 163         print("listing", lst)
 164
 165         # initial values in GPR regfile
 166         initial_regs = [0] * 32
 167         idxs = [1, 0, 5, 2, 4, 3]  # random enough
 168         for i in range(6):
 169             initial_regs[16+i] = idxs[i]
 170             initial_regs[i] = i
 171
 172         # SVSTATE vl=10
 173         svstate = SVP64State()
 174         svstate.vl = 6  # VL
 175         svstate.maxvl = 6  # MAXVL
 176         print("SVSTATE", bin(svstate.asint()))
 177
 178         # copy before running
 179         expected_regs = deepcopy(initial_regs)
 180         for i in range(6):
 181             RA = initial_regs[0+idxs[i]]
 182             RB = initial_regs[0+i]
 183             expected_regs[i+8] = RA+RB
 184             print("expected", i, expected_regs[i+8])
 185
 186         with Program(lst, bigendian=False) as program:
 187             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 188
 189             print(sim.spr)
 190             SVSHAPE0 = sim.spr['SVSHAPE0']
 191             print("SVSTATE after", bin(sim.svstate.asint()))
 192             print("        vl", bin(sim.svstate.vl))
 193             print("        mvl", bin(sim.svstate.maxvl))
 194             print("    srcstep", bin(sim.svstate.srcstep))
 195             print("    dststep", bin(sim.svstate.dststep))
 196             print("      RMpst", bin(sim.svstate.RMpst))
 197             print("       SVme", bin(sim.svstate.SVme))
 198             print("        mo0", bin(sim.svstate.mo0))
 199             print("        mo1", bin(sim.svstate.mo1))
 200             print("        mi0", bin(sim.svstate.mi0))
 201             print("        mi1", bin(sim.svstate.mi1))
 202             print("        mi2", bin(sim.svstate.mi2))
 203             print("STATE0svgpr", hex(SVSHAPE0.svgpr))
 204             print(sim.gpr.dump())
 205             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
 206             self.assertEqual(sim.svstate.SVme, 0b00001)  # same as rmm
 207             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 208             self.assertEqual(sim.svstate.mi0, 0)
 209             self.assertEqual(sim.svstate.mi1, 0)
 210             self.assertEqual(sim.svstate.mi2, 0)
 211             self.assertEqual(sim.svstate.mo0, 0)
 212             self.assertEqual(sim.svstate.mo1, 0)
 213             self.assertEqual(SVSHAPE0.svgpr, 16)  # SVG is shifted up by 1
 214             for i in range(1, 4):
 215                 shape = sim.spr['SVSHAPE%d' % i]
 216                 self.assertEqual(shape.svgpr, 0)
 217             self._check_regs(sim, expected_regs)
 218
 219     def test_1_sv_index_add(self):
 220         """sets VL=6 (via SVSTATE) then does modulo 3 svindex, and an add.
 221
 222         only RA is re-mapped via Indexing, not RB or RT
 223         """
 224         isa = SVP64Asm(['svindex 8, 1, 3, 0, 0, 0, 0',
 225                         'sv.add *8, *0, *0',
 226                         ])
 227         lst = list(isa)
 228         print("listing", lst)
 229
 230         # initial values in GPR regfile
 231         initial_regs = [0] * 32
 232         idxs = [1, 0, 5, 2, 4, 3]  # random enough
 233         for i in range(6):
 234             initial_regs[16+i] = idxs[i]
 235             initial_regs[i] = i
 236
 237         # SVSTATE vl=10
 238         svstate = SVP64State()
 239         svstate.vl = 6  # VL
 240         svstate.maxvl = 6  # MAXVL
 241         print("SVSTATE", bin(svstate.asint()))
 242
 243         # copy before running
 244         expected_regs = deepcopy(initial_regs)
 245         for i in range(6):
 246             RA = initial_regs[0+idxs[i % 3]]  # modulo 3 but still indexed
 247             RB = initial_regs[0+i]
 248             expected_regs[i+8] = RA+RB
 249             print("expected", i, expected_regs[i+8])
 250
 251         with Program(lst, bigendian=False) as program:
 252             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 253
 254             print(sim.spr)
 255             SVSHAPE0 = sim.spr['SVSHAPE0']
 256             print("SVSTATE after", bin(sim.svstate.asint()))
 257             print("        vl", bin(sim.svstate.vl))
 258             print("        mvl", bin(sim.svstate.maxvl))
 259             print("    srcstep", bin(sim.svstate.srcstep))
 260             print("    dststep", bin(sim.svstate.dststep))
 261             print("      RMpst", bin(sim.svstate.RMpst))
 262             print("       SVme", bin(sim.svstate.SVme))
 263             print("        mo0", bin(sim.svstate.mo0))
 264             print("        mo1", bin(sim.svstate.mo1))
 265             print("        mi0", bin(sim.svstate.mi0))
 266             print("        mi1", bin(sim.svstate.mi1))
 267             print("        mi2", bin(sim.svstate.mi2))
 268             print("STATE0svgpr", hex(SVSHAPE0.svgpr))
 269             print("STATE0 xdim", SVSHAPE0.xdimsz)
 270             print("STATE0 ydim", SVSHAPE0.ydimsz)
 271             print("STATE0 skip", bin(SVSHAPE0.skip))
 272             print("STATE0  inv", SVSHAPE0.invxyz)
 273             print("STATE0order", SVSHAPE0.order)
 274             print(sim.gpr.dump())
 275             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
 276             self.assertEqual(sim.svstate.SVme, 0b00001)  # same as rmm
 277             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 278             self.assertEqual(sim.svstate.mi0, 0)
 279             self.assertEqual(sim.svstate.mi1, 0)
 280             self.assertEqual(sim.svstate.mi2, 0)
 281             self.assertEqual(sim.svstate.mo0, 0)
 282             self.assertEqual(sim.svstate.mo1, 0)
 283             self.assertEqual(SVSHAPE0.svgpr, 16)  # SVG is shifted up by 1
 284             for i in range(1, 4):
 285                 shape = sim.spr['SVSHAPE%d' % i]
 286                 self.assertEqual(shape.svgpr, 0)
 287             self._check_regs(sim, expected_regs)
 288
 289     def test_2_sv_index_add(self):
 290         """sets VL=6 (via SVSTATE) then does 2D remapped svindex, and an add.
 291
 292         dim=3,yx=1
 293         only RA is re-mapped via Indexing, not RB or RT
 294         """
 295         isa = SVP64Asm(['svindex 8, 1, 3, 0, 1, 0, 0',
 296                         'sv.add *8, *0, *0',
 297                         ])
 298         lst = list(isa)
 299         print("listing", lst)
 300
 301         # initial values in GPR regfile
 302         initial_regs = [0] * 32
 303         idxs = [1, 0, 5, 2, 4, 3]  # random enough
 304         for i in range(6):
 305             initial_regs[16+i] = idxs[i]
 306             initial_regs[i] = i
 307
 308         # SVSTATE vl=10
 309         svstate = SVP64State()
 310         svstate.vl = 6  # VL
 311         svstate.maxvl = 6  # MAXVL
 312         print("SVSTATE", bin(svstate.asint()))
 313
 314         # copy before running
 315         expected_regs = deepcopy(initial_regs)
 316         for i in range(6):
 317             xi = i % 3
 318             yi = i // 3
 319             remap = yi+xi*2
 320             RA = initial_regs[0+idxs[remap]]  # modulo 3 but still indexed
 321             RB = initial_regs[0+i]
 322             expected_regs[i+8] = RA+RB
 323             print("expected", i, expected_regs[i+8])
 324
 325         with Program(lst, bigendian=False) as program:
 326             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 327
 328             print(sim.spr)
 329             SVSHAPE0 = sim.spr['SVSHAPE0']
 330             print("SVSTATE after", bin(sim.svstate.asint()))
 331             print("        vl", bin(sim.svstate.vl))
 332             print("        mvl", bin(sim.svstate.maxvl))
 333             print("    srcstep", bin(sim.svstate.srcstep))
 334             print("    dststep", bin(sim.svstate.dststep))
 335             print("      RMpst", bin(sim.svstate.RMpst))
 336             print("       SVme", bin(sim.svstate.SVme))
 337             print("        mo0", bin(sim.svstate.mo0))
 338             print("        mo1", bin(sim.svstate.mo1))
 339             print("        mi0", bin(sim.svstate.mi0))
 340             print("        mi1", bin(sim.svstate.mi1))
 341             print("        mi2", bin(sim.svstate.mi2))
 342             print("STATE0svgpr", hex(SVSHAPE0.svgpr))
 343             print("STATE0 xdim", SVSHAPE0.xdimsz)
 344             print("STATE0 ydim", SVSHAPE0.ydimsz)
 345             print("STATE0 skip", bin(SVSHAPE0.skip))
 346             print("STATE0  inv", SVSHAPE0.invxyz)
 347             print("STATE0order", SVSHAPE0.order)
 348             print(sim.gpr.dump())
 349             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
 350             self.assertEqual(sim.svstate.SVme, 0b00001)  # same as rmm
 351             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 352             self.assertEqual(sim.svstate.mi0, 0)
 353             self.assertEqual(sim.svstate.mi1, 0)
 354             self.assertEqual(sim.svstate.mi2, 0)
 355             self.assertEqual(sim.svstate.mo0, 0)
 356             self.assertEqual(sim.svstate.mo1, 0)
 357             self.assertEqual(SVSHAPE0.svgpr, 16)  # SVG is shifted up by 1
 358             for i in range(1, 4):
 359                 shape = sim.spr['SVSHAPE%d' % i]
 360                 self.assertEqual(shape.svgpr, 0)
 361             self._check_regs(sim, expected_regs)
 362
 363     def test_3_sv_index_add_elwidth(self):
 364         """sets VL=6 (via SVSTATE) then does svindex with elwidth=8, and an add.
 365
 366         only RA is re-mapped via Indexing, not RB or RT
 367         """
 368         isa = SVP64Asm(['svindex 8, 1, 1, 3, 0, 0, 0',
 369                         'sv.add *8, *0, *0',
 370                         ])
 371         lst = list(isa)
 372         print("listing", lst)
 373
 374         # initial values in GPR regfile
 375         initial_regs = [0] * 32
 376         idxs = [1, 0, 5, 2, 4, 3]  # random enough
 377         for i in range(6):
 378             # 8-bit indices starting at reg 16
 379             set_masked_reg(initial_regs, 16, i, ew_bits=8, value=idxs[i])
 380             initial_regs[i] = i
 381
 382         # SVSTATE vl=10
 383         svstate = SVP64State()
 384         svstate.vl = 6  # VL
 385         svstate.maxvl = 6  # MAXVL
 386         print("SVSTATE", bin(svstate.asint()))
 387
 388         # copy before running
 389         expected_regs = deepcopy(initial_regs)
 390         for i in range(6):
 391             RA = initial_regs[0+idxs[i]]
 392             RB = initial_regs[0+i]
 393             expected_regs[i+8] = RA+RB
 394             print("expected", i, expected_regs[i+8])
 395
 396         with Program(lst, bigendian=False) as program:
 397             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 398
 399             print(sim.spr)
 400             SVSHAPE0 = sim.spr['SVSHAPE0']
 401             print("SVSTATE after", bin(sim.svstate.asint()))
 402             print("        vl", bin(sim.svstate.vl))
 403             print("        mvl", bin(sim.svstate.maxvl))
 404             print("    srcstep", bin(sim.svstate.srcstep))
 405             print("    dststep", bin(sim.svstate.dststep))
 406             print("      RMpst", bin(sim.svstate.RMpst))
 407             print("       SVme", bin(sim.svstate.SVme))
 408             print("        mo0", bin(sim.svstate.mo0))
 409             print("        mo1", bin(sim.svstate.mo1))
 410             print("        mi0", bin(sim.svstate.mi0))
 411             print("        mi1", bin(sim.svstate.mi1))
 412             print("        mi2", bin(sim.svstate.mi2))
 413             print("STATE0svgpr", hex(SVSHAPE0.svgpr))
 414             print(sim.gpr.dump())
 415             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
 416             self.assertEqual(sim.svstate.SVme, 0b00001)  # same as rmm
 417             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 418             self.assertEqual(sim.svstate.mi0, 0)
 419             self.assertEqual(sim.svstate.mi1, 0)
 420             self.assertEqual(sim.svstate.mi2, 0)
 421             self.assertEqual(sim.svstate.mo0, 0)
 422             self.assertEqual(sim.svstate.mo1, 0)
 423             self.assertEqual(SVSHAPE0.svgpr, 16)  # SVG is shifted up by 1
 424             for i in range(1, 4):
 425                 shape = sim.spr['SVSHAPE%d' % i]
 426                 self.assertEqual(shape.svgpr, 0)
 427             self._check_regs(sim, expected_regs)
 428
 429     def run_tst_program(self, prog, initial_regs=None,
 430                         svstate=None):
 431         if initial_regs is None:
 432             initial_regs = [0] * 32
 433         simulator = run_tst(prog, initial_regs, svstate=svstate)
 434         simulator.gpr.dump()
 435         return simulator
 436
 437
 438 if __name__ == "__main__":
 439     unittest.main()