1 """SVP64 unit test for svindex
2 svindex SVG,rmm,SVd,ew,yx,mm,sk
4 from nmigen
import Module
, Signal
5 from nmigen
.sim
import Simulator
, Delay
, Settle
6 from nmutil
.formaltest
import FHDLTestCase
8 from openpower
.decoder
.isa
.caller
import ISACaller
9 from openpower
.decoder
.power_decoder
import (create_pdecode
)
10 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
11 from openpower
.simulator
.program
import Program
12 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
, CRFields
13 from openpower
.decoder
.selectable_int
import SelectableInt
14 from openpower
.decoder
.orderedset
import OrderedSet
15 from openpower
.decoder
.isa
.all
import ISA
16 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
17 from openpower
.sv
.trans
.svp64
import SVP64Asm
18 from openpower
.consts
import SVP64CROffs
19 from copy
import deepcopy
22 class SVSTATETestCase(FHDLTestCase
):
24 def _check_regs(self
, sim
, expected
):
28 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64),
29 "GPR %d %x expected %x" % (i
, sim
.gpr(i
).value
, expected
[i
]))
31 def test_0_sv_index(self
):
32 """sets VL=10 (via SVSTATE) then does svindex mm=0, checks SPRs after
34 isa
= SVP64Asm(['svindex 1, 15, 5, 0, 0, 0, 0'
37 print ("listing", lst
)
39 # initial values in GPR regfile
40 initial_regs
= [0] * 32
41 initial_regs
[9] = 0x1234
42 initial_regs
[10] = 0x1111
43 initial_regs
[5] = 0x4321
44 initial_regs
[6] = 0x2223
47 svstate
= SVP64State()
49 svstate
.maxvl
= 10 # MAXVL
50 print ("SVSTATE", bin(svstate
.asint()))
53 expected_regs
= deepcopy(initial_regs
)
54 #expected_regs[1] = 0x3334
56 with
Program(lst
, bigendian
=False) as program
:
57 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
58 self
._check
_regs
(sim
, expected_regs
)
61 SVSHAPE0
= sim
.spr
['SVSHAPE0']
62 print ("SVSTATE after", bin(sim
.svstate
.asint()))
63 print (" vl", bin(sim
.svstate
.vl
))
64 print (" mvl", bin(sim
.svstate
.maxvl
))
65 print (" srcstep", bin(sim
.svstate
.srcstep
))
66 print (" dststep", bin(sim
.svstate
.dststep
))
67 print (" RMpst", bin(sim
.svstate
.RMpst
))
68 print (" SVme", bin(sim
.svstate
.SVme
))
69 print (" mo0", bin(sim
.svstate
.mo0
))
70 print (" mo1", bin(sim
.svstate
.mo1
))
71 print (" mi0", bin(sim
.svstate
.mi0
))
72 print (" mi1", bin(sim
.svstate
.mi1
))
73 print (" mi2", bin(sim
.svstate
.mi2
))
74 print ("STATE0svgpr", hex(SVSHAPE0
.svgpr
))
75 print ("STATE0 xdim", SVSHAPE0
.xdimsz
)
76 print ("STATE0 ydim", SVSHAPE0
.ydimsz
)
77 print ("STATE0 skip", bin(SVSHAPE0
.skip
))
78 print ("STATE0 inv", SVSHAPE0
.invxyz
)
79 print ("STATE0order", SVSHAPE0
.order
)
80 self
.assertEqual(sim
.svstate
.RMpst
, 0) # mm=0 so persist=0
81 self
.assertEqual(sim
.svstate
.SVme
, 0b01111) # same as rmm
82 # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
83 self
.assertEqual(sim
.svstate
.mi0
, 0)
84 self
.assertEqual(sim
.svstate
.mi1
, 1)
85 self
.assertEqual(sim
.svstate
.mi2
, 2)
86 self
.assertEqual(sim
.svstate
.mo0
, 3)
87 self
.assertEqual(sim
.svstate
.mo1
, 0)
89 shape
= sim
.spr
['SVSHAPE%d' % i
]
90 self
.assertEqual(shape
.svgpr
, 2) # SVG is shifted up by 1
92 def test_1_sv_index(self
):
93 """sets VL=10 (via SVSTATE) then does svindex mm=1, checks SPRs after
95 # rmm: bits 0-2 (MSB0) are 0b011 and bits 3-4 are 0b10.
96 # therefore rmm is 0b011 || 0b10 --> 0b01110 -> 14
97 isa
= SVP64Asm(['svindex 1, 14, 5, 0, 0, 1, 0'
100 print ("listing", lst
)
102 # initial values in GPR regfile
103 initial_regs
= [0] * 32
104 initial_regs
[9] = 0x1234
105 initial_regs
[10] = 0x1111
106 initial_regs
[5] = 0x4321
107 initial_regs
[6] = 0x2223
110 svstate
= SVP64State()
112 svstate
.maxvl
= 10 # MAXVL
113 print ("SVSTATE", bin(svstate
.asint()))
115 # copy before running
116 expected_regs
= deepcopy(initial_regs
)
117 #expected_regs[1] = 0x3334
119 with
Program(lst
, bigendian
=False) as program
:
120 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
121 self
._check
_regs
(sim
, expected_regs
)
124 SVSHAPE2
= sim
.spr
['SVSHAPE2']
125 print ("SVSTATE after", bin(sim
.svstate
.asint()))
126 print (" vl", bin(sim
.svstate
.vl
))
127 print (" mvl", bin(sim
.svstate
.maxvl
))
128 print (" srcstep", bin(sim
.svstate
.srcstep
))
129 print (" dststep", bin(sim
.svstate
.dststep
))
130 print (" RMpst", bin(sim
.svstate
.RMpst
))
131 print (" SVme", bin(sim
.svstate
.SVme
))
132 print (" mo0", bin(sim
.svstate
.mo0
))
133 print (" mo1", bin(sim
.svstate
.mo1
))
134 print (" mi0", bin(sim
.svstate
.mi0
))
135 print (" mi1", bin(sim
.svstate
.mi1
))
136 print (" mi2", bin(sim
.svstate
.mi2
))
137 print ("STATE2svgpr", hex(SVSHAPE2
.svgpr
))
138 print ("STATE2 xdim", SVSHAPE2
.xdimsz
)
139 print ("STATE2 ydim", SVSHAPE2
.ydimsz
)
140 print ("STATE2 skip", bin(SVSHAPE2
.skip
))
141 print ("STATE2 inv", SVSHAPE2
.invxyz
)
142 print ("STATE2order", SVSHAPE2
.order
)
143 self
.assertEqual(sim
.svstate
.RMpst
, 1) # mm=1 so persist=1
144 # rmm is 0b01110 which means mo0 = 2
145 self
.assertEqual(sim
.svstate
.mi0
, 0)
146 self
.assertEqual(sim
.svstate
.mi1
, 0)
147 self
.assertEqual(sim
.svstate
.mi2
, 0)
148 self
.assertEqual(sim
.svstate
.mo0
, 2)
149 self
.assertEqual(sim
.svstate
.mo1
, 0)
150 # and mo0 should be activated
151 self
.assertEqual(sim
.svstate
.SVme
, 0b01000)
152 # now check the SVSHAPEs. 2 was the one targetted
153 self
.assertEqual(SVSHAPE2
.svgpr
, 2) # SVG is shifted up by 1
154 self
.assertEqual(SVSHAPE2
.xdimsz
, 5) # SHAPE2 xdim set to 5
155 self
.assertEqual(SVSHAPE2
.ydimsz
, 1) # SHAPE2 ydim 1
156 # all others must be zero
158 shape
= sim
.spr
['SVSHAPE%d' % i
]
159 self
.assertEqual(shape
.asint(), 0) # all others zero
161 def test_0_sv_index_add(self
):
162 """sets VL=6 (via SVSTATE) then does svindex, and an add.
164 only RA is re-mapped via Indexing, not RB or RT
166 isa
= SVP64Asm(['svindex 8, 1, 1, 0, 0, 0, 0',
170 print ("listing", lst
)
172 # initial values in GPR regfile
173 initial_regs
= [0] * 32
174 idxs
= [1, 0, 5, 2, 4, 3] # random enough
176 initial_regs
[16+i
] = idxs
[i
]
180 svstate
= SVP64State()
182 svstate
.maxvl
= 6 # MAXVL
183 print ("SVSTATE", bin(svstate
.asint()))
185 # copy before running
186 expected_regs
= deepcopy(initial_regs
)
188 RA
= initial_regs
[0+idxs
[i
]]
189 RB
= initial_regs
[0+i
]
190 expected_regs
[i
+8] = RA
+RB
191 print ("expected", i
, expected_regs
[i
+8])
193 with
Program(lst
, bigendian
=False) as program
:
194 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
197 SVSHAPE0
= sim
.spr
['SVSHAPE0']
198 print ("SVSTATE after", bin(sim
.svstate
.asint()))
199 print (" vl", bin(sim
.svstate
.vl
))
200 print (" mvl", bin(sim
.svstate
.maxvl
))
201 print (" srcstep", bin(sim
.svstate
.srcstep
))
202 print (" dststep", bin(sim
.svstate
.dststep
))
203 print (" RMpst", bin(sim
.svstate
.RMpst
))
204 print (" SVme", bin(sim
.svstate
.SVme
))
205 print (" mo0", bin(sim
.svstate
.mo0
))
206 print (" mo1", bin(sim
.svstate
.mo1
))
207 print (" mi0", bin(sim
.svstate
.mi0
))
208 print (" mi1", bin(sim
.svstate
.mi1
))
209 print (" mi2", bin(sim
.svstate
.mi2
))
210 print ("STATE0svgpr", hex(SVSHAPE0
.svgpr
))
211 print (sim
.gpr
.dump())
212 self
.assertEqual(sim
.svstate
.RMpst
, 0) # mm=0 so persist=0
213 self
.assertEqual(sim
.svstate
.SVme
, 0b00001) # same as rmm
214 # rmm is 0b00001 which means mi0=0 and all others inactive (0)
215 self
.assertEqual(sim
.svstate
.mi0
, 0)
216 self
.assertEqual(sim
.svstate
.mi1
, 0)
217 self
.assertEqual(sim
.svstate
.mi2
, 0)
218 self
.assertEqual(sim
.svstate
.mo0
, 0)
219 self
.assertEqual(sim
.svstate
.mo1
, 0)
220 self
.assertEqual(SVSHAPE0
.svgpr
, 16) # SVG is shifted up by 1
222 shape
= sim
.spr
['SVSHAPE%d' % i
]
223 self
.assertEqual(shape
.svgpr
, 0)
224 self
._check
_regs
(sim
, expected_regs
)
226 def test_1_sv_index_add(self
):
227 """sets VL=6 (via SVSTATE) then does modulo 3 svindex, and an add.
229 only RA is re-mapped via Indexing, not RB or RT
231 isa
= SVP64Asm(['svindex 8, 1, 3, 0, 0, 0, 0',
235 print ("listing", lst
)
237 # initial values in GPR regfile
238 initial_regs
= [0] * 32
239 idxs
= [1, 0, 5, 2, 4, 3] # random enough
241 initial_regs
[16+i
] = idxs
[i
]
245 svstate
= SVP64State()
247 svstate
.maxvl
= 6 # MAXVL
248 print ("SVSTATE", bin(svstate
.asint()))
250 # copy before running
251 expected_regs
= deepcopy(initial_regs
)
253 RA
= initial_regs
[0+idxs
[i
%3]] # modulo 3 but still indexed
254 RB
= initial_regs
[0+i
]
255 expected_regs
[i
+8] = RA
+RB
256 print ("expected", i
, expected_regs
[i
+8])
258 with
Program(lst
, bigendian
=False) as program
:
259 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
262 SVSHAPE0
= sim
.spr
['SVSHAPE0']
263 print ("SVSTATE after", bin(sim
.svstate
.asint()))
264 print (" vl", bin(sim
.svstate
.vl
))
265 print (" mvl", bin(sim
.svstate
.maxvl
))
266 print (" srcstep", bin(sim
.svstate
.srcstep
))
267 print (" dststep", bin(sim
.svstate
.dststep
))
268 print (" RMpst", bin(sim
.svstate
.RMpst
))
269 print (" SVme", bin(sim
.svstate
.SVme
))
270 print (" mo0", bin(sim
.svstate
.mo0
))
271 print (" mo1", bin(sim
.svstate
.mo1
))
272 print (" mi0", bin(sim
.svstate
.mi0
))
273 print (" mi1", bin(sim
.svstate
.mi1
))
274 print (" mi2", bin(sim
.svstate
.mi2
))
275 print ("STATE0svgpr", hex(SVSHAPE0
.svgpr
))
276 print ("STATE0 xdim", SVSHAPE0
.xdimsz
)
277 print ("STATE0 ydim", SVSHAPE0
.ydimsz
)
278 print ("STATE0 skip", bin(SVSHAPE0
.skip
))
279 print ("STATE0 inv", SVSHAPE0
.invxyz
)
280 print ("STATE0order", SVSHAPE0
.order
)
281 print (sim
.gpr
.dump())
282 self
.assertEqual(sim
.svstate
.RMpst
, 0) # mm=0 so persist=0
283 self
.assertEqual(sim
.svstate
.SVme
, 0b00001) # same as rmm
284 # rmm is 0b00001 which means mi0=0 and all others inactive (0)
285 self
.assertEqual(sim
.svstate
.mi0
, 0)
286 self
.assertEqual(sim
.svstate
.mi1
, 0)
287 self
.assertEqual(sim
.svstate
.mi2
, 0)
288 self
.assertEqual(sim
.svstate
.mo0
, 0)
289 self
.assertEqual(sim
.svstate
.mo1
, 0)
290 self
.assertEqual(SVSHAPE0
.svgpr
, 16) # SVG is shifted up by 1
292 shape
= sim
.spr
['SVSHAPE%d' % i
]
293 self
.assertEqual(shape
.svgpr
, 0)
294 self
._check
_regs
(sim
, expected_regs
)
296 def test_2_sv_index_add(self
):
297 """sets VL=6 (via SVSTATE) then does 2D remapped svindex, and an add.
300 only RA is re-mapped via Indexing, not RB or RT
302 isa
= SVP64Asm(['svindex 8, 1, 3, 0, 1, 0, 0',
306 print ("listing", lst
)
308 # initial values in GPR regfile
309 initial_regs
= [0] * 32
310 idxs
= [1, 0, 5, 2, 4, 3] # random enough
312 initial_regs
[16+i
] = idxs
[i
]
316 svstate
= SVP64State()
318 svstate
.maxvl
= 6 # MAXVL
319 print ("SVSTATE", bin(svstate
.asint()))
321 # copy before running
322 expected_regs
= deepcopy(initial_regs
)
327 RA
= initial_regs
[0+idxs
[remap
]] # modulo 3 but still indexed
328 RB
= initial_regs
[0+i
]
329 expected_regs
[i
+8] = RA
+RB
330 print ("expected", i
, expected_regs
[i
+8])
332 with
Program(lst
, bigendian
=False) as program
:
333 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
336 SVSHAPE0
= sim
.spr
['SVSHAPE0']
337 print ("SVSTATE after", bin(sim
.svstate
.asint()))
338 print (" vl", bin(sim
.svstate
.vl
))
339 print (" mvl", bin(sim
.svstate
.maxvl
))
340 print (" srcstep", bin(sim
.svstate
.srcstep
))
341 print (" dststep", bin(sim
.svstate
.dststep
))
342 print (" RMpst", bin(sim
.svstate
.RMpst
))
343 print (" SVme", bin(sim
.svstate
.SVme
))
344 print (" mo0", bin(sim
.svstate
.mo0
))
345 print (" mo1", bin(sim
.svstate
.mo1
))
346 print (" mi0", bin(sim
.svstate
.mi0
))
347 print (" mi1", bin(sim
.svstate
.mi1
))
348 print (" mi2", bin(sim
.svstate
.mi2
))
349 print ("STATE0svgpr", hex(SVSHAPE0
.svgpr
))
350 print ("STATE0 xdim", SVSHAPE0
.xdimsz
)
351 print ("STATE0 ydim", SVSHAPE0
.ydimsz
)
352 print ("STATE0 skip", bin(SVSHAPE0
.skip
))
353 print ("STATE0 inv", SVSHAPE0
.invxyz
)
354 print ("STATE0order", SVSHAPE0
.order
)
355 print (sim
.gpr
.dump())
356 self
.assertEqual(sim
.svstate
.RMpst
, 0) # mm=0 so persist=0
357 self
.assertEqual(sim
.svstate
.SVme
, 0b00001) # same as rmm
358 # rmm is 0b00001 which means mi0=0 and all others inactive (0)
359 self
.assertEqual(sim
.svstate
.mi0
, 0)
360 self
.assertEqual(sim
.svstate
.mi1
, 0)
361 self
.assertEqual(sim
.svstate
.mi2
, 0)
362 self
.assertEqual(sim
.svstate
.mo0
, 0)
363 self
.assertEqual(sim
.svstate
.mo1
, 0)
364 self
.assertEqual(SVSHAPE0
.svgpr
, 16) # SVG is shifted up by 1
366 shape
= sim
.spr
['SVSHAPE%d' % i
]
367 self
.assertEqual(shape
.svgpr
, 0)
368 self
._check
_regs
(sim
, expected_regs
)
370 def run_tst_program(self
, prog
, initial_regs
=None,
372 if initial_regs
is None:
373 initial_regs
= [0] * 32
374 simulator
= run_tst(prog
, initial_regs
, svstate
=svstate
)
379 if __name__
== "__main__":