src/openpower/decoder/isa/test_caller_svindex.py

   1 """SVP64 unit test for svindex
   2 svindex SVG,rmm,SVd,ew,yx,mr,sk
   3 """
   4 from nmigen import Module, Signal
   5 from nmigen.back.pysim import Simulator, Delay, Settle
   6 from nmutil.formaltest import FHDLTestCase
   7 import unittest
   8 from openpower.decoder.isa.caller import ISACaller
   9 from openpower.decoder.power_decoder import (create_pdecode)
  10 from openpower.decoder.power_decoder2 import (PowerDecode2)
  11 from openpower.simulator.program import Program
  12 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  13 from openpower.decoder.selectable_int import SelectableInt
  14 from openpower.decoder.orderedset import OrderedSet
  15 from openpower.decoder.isa.all import ISA
  16 from openpower.decoder.isa.test_caller import Register, run_tst
  17 from openpower.sv.trans.svp64 import SVP64Asm
  18 from openpower.consts import SVP64CROffs
  19 from copy import deepcopy
  20
  21
  22 class SVSTATETestCase(FHDLTestCase):
  23
  24     def _check_regs(self, sim, expected):
  25         print ("GPR")
  26         sim.gpr.dump()
  27         for i in range(32):
  28             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  29
  30     def test_sv_index(self):
  31         """sets VL=10 (via SVSTATE) then does svindex, checks SPRs after
  32         """
  33         isa = SVP64Asm(['svindex 1, 15, 5, 0, 0, 0, 0'
  34                        ])
  35         lst = list(isa)
  36         print ("listing", lst)
  37
  38         # initial values in GPR regfile
  39         initial_regs = [0] * 32
  40         initial_regs[9] = 0x1234
  41         initial_regs[10] = 0x1111
  42         initial_regs[5] = 0x4321
  43         initial_regs[6] = 0x2223
  44
  45         # SVSTATE vl=10
  46         svstate = SVP64State()
  47         svstate.vl = 10 # VL
  48         svstate.maxvl = 10 # MAXVL
  49         print ("SVSTATE", bin(svstate.asint()))
  50
  51         # copy before running
  52         expected_regs = deepcopy(initial_regs)
  53         #expected_regs[1] = 0x3334
  54
  55         with Program(lst, bigendian=False) as program:
  56             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
  57             self._check_regs(sim, expected_regs)
  58
  59             print (sim.spr)
  60             SVSHAPE0 = sim.spr['SVSHAPE0']
  61             print ("SVSTATE after", bin(sim.svstate.asint()))
  62             print ("        vl", bin(sim.svstate.vl))
  63             print ("        mvl", bin(sim.svstate.maxvl))
  64             print ("    srcstep", bin(sim.svstate.srcstep))
  65             print ("    dststep", bin(sim.svstate.dststep))
  66             print ("      RMpst", bin(sim.svstate.RMpst))
  67             print ("       SVme", bin(sim.svstate.SVme))
  68             print ("        mo0", bin(sim.svstate.mo0))
  69             print ("        mo1", bin(sim.svstate.mo1))
  70             print ("        mi0", bin(sim.svstate.mi0))
  71             print ("        mi1", bin(sim.svstate.mi1))
  72             print ("        mi2", bin(sim.svstate.mi2))
  73             print ("STATE0svgpr", hex(SVSHAPE0.svgpr))
  74             self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
  75             self.assertEqual(sim.svstate.SVme, 0b01111) # same as rmm
  76             # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
  77             self.assertEqual(sim.svstate.mi0, 0)
  78             self.assertEqual(sim.svstate.mi1, 1)
  79             self.assertEqual(sim.svstate.mi2, 2)
  80             self.assertEqual(sim.svstate.mo0, 3)
  81             self.assertEqual(sim.svstate.mo1, 0)
  82             for i in range(4):
  83                 shape = sim.spr['SVSHAPE%d' % i]
  84                 self.assertEqual(shape.svgpr, 2) # SVG is shifted up by 1
  85
  86     def run_tst_program(self, prog, initial_regs=None,
  87                               svstate=None):
  88         if initial_regs is None:
  89             initial_regs = [0] * 32
  90         simulator = run_tst(prog, initial_regs, svstate=svstate)
  91         simulator.gpr.dump()
  92         return simulator
  93
  94
  95 if __name__ == "__main__":
  96     unittest.main()
  97