src/openpower/decoder/isa/test_runner.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Settle
   3 from openpower.decoder.isa.caller import ISACaller
   4 from openpower.decoder.power_decoder import create_pdecode
   5 from openpower.decoder.power_decoder2 import (PowerDecode2)
   6 from openpower.simulator.program import Program
   7 from openpower.decoder.isa.caller import ISACaller, inject
   8 from openpower.decoder.isa.all import ISA
   9 from openpower.test.state import TestState
  10 from nmutil.formaltest import FHDLTestCase
  11
  12
  13 class Register:
  14     def __init__(self, num):
  15         self.num = num
  16
  17
  18 class ISATestRunner(FHDLTestCase):
  19     def __init__(self, tst_data, include_fp=True):
  20         super().__init__("run_all")
  21         self.test_data = tst_data
  22         self.include_fp = include_fp
  23
  24     def run_all(self):
  25         m = Module()
  26         comb = m.d.comb
  27         instruction = Signal(32)
  28
  29         pdecode = create_pdecode(include_fp=self.include_fp)
  30         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  31
  32         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  33         sim = Simulator(m)
  34
  35         def process():
  36
  37             for test in self.test_data:
  38
  39                 with self.subTest(test.name):
  40                     generator = test.program
  41
  42                     gen = list(generator.generate_instructions())
  43                     insncode = generator.assembly.splitlines()
  44                     instructions = list(zip(gen, insncode))
  45
  46                     simulator = ISA(pdecode2, test.regs,
  47                                     test.sprs,
  48                                     test.cr,
  49                                     initial_insns=gen, respect_pc=True,
  50                                     initial_svstate=test.svstate,
  51                                     initial_mem=test.mem,
  52                                     fpregfile=None,
  53                                     disassembly=insncode,
  54                                     bigendian=0,
  55                                     mmu=False)
  56
  57                     print ("GPRs")
  58                     simulator.gpr.dump()
  59                     print ("FPRs")
  60                     simulator.fpr.dump()
  61
  62                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
  63                     pc = simulator.pc.CIA.value
  64                     index = pc//4
  65                     while index < len(instructions):
  66                         print("instr pc", pc)
  67                         try:
  68                             yield from simulator.setup_one()
  69                         except KeyError:  # instruction not in imem: stop
  70                             break
  71                         yield Settle()
  72
  73                         ins, code = instructions[index]
  74                         print("    0x{:X}".format(ins & 0xffffffff))
  75                         opname = code.split(' ')[0]
  76                         print(code, opname)
  77
  78                         # ask the decoder to decode this binary data (endian'd)
  79                         yield from simulator.execute_one()
  80                         pc = simulator.pc.CIA.value
  81                         index = pc//4
  82
  83         # run simulator multiple times, using the same PowerDecoder2,
  84         # with multiple sub-tests
  85         sim.add_process(process)
  86         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  87                            traces=[]):
  88             sim.run()
  89
  90
  91 def check_regs(dut, sim, expected, test, code):
  92     # create the two states and compare
  93     testdic = {'sim': sim, 'expected': expected}
  94     yield from teststate_check_regs(dut, testdic, test, code)
  95
  96
  97 def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
  98                                      initial_cr=0, mem=None,
  99                                      initial_fprs=None,
 100                                      pdecode2=None,
 101                                      state=None): # (dut, code)
 102     if initial_sprs is None:
 103         initial_sprs = {}
 104     m = Module()
 105     comb = m.d.comb
 106     instruction = Signal(32)
 107
 108     if pdecode2 is None:
 109         pdecode = create_pdecode(include_fp=initial_fprs is not None)
 110         pdecode2 = PowerDecode2(pdecode)
 111     m.submodules.pdecode2 = pdecode2
 112
 113     gen = list(generator.generate_instructions())
 114     insncode = generator.assembly.splitlines()
 115     instructions = list(zip(gen, insncode))
 116
 117     simulator = ISA(pdecode2, initial_regs, initial_sprs, initial_cr,
 118                     initial_insns=gen, respect_pc=True,
 119                     initial_svstate=svstate,
 120                     initial_mem=mem,
 121                     fpregfile=initial_fprs,
 122                     disassembly=insncode,
 123                     bigendian=0,
 124                     mmu=mmu)
 125     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 126     sim = Simulator(m)
 127
 128     process_state = state
 129
 130     def process():
 131
 132         print ("GPRs")
 133         simulator.gpr.dump()
 134         print ("FPRs")
 135         simulator.fpr.dump()
 136
 137         yield pdecode2.dec.bigendian.eq(0)  # little / big?
 138         pc = simulator.pc.CIA.value
 139         index = pc//4
 140         while index < len(instructions):
 141             print("instr pc", pc)
 142             try:
 143                 yield from simulator.setup_one()
 144             except KeyError:  # indicates instruction not in imem: stop
 145                 break
 146             yield Settle()
 147
 148             ins, code = instructions[index]
 149             print("    0x{:X}".format(ins & 0xffffffff))
 150             opname = code.split(' ')[0]
 151             print(code, opname)
 152
 153             # ask the decoder to decode this binary data (endian'd)
 154             yield from simulator.execute_one()
 155             pc = simulator.pc.CIA.value
 156             index = pc//4
 157
 158         # use this to test against expected (static) results at end of run
 159         if process_state is not None:
 160             (dut, code) = process_state
 161             simulator.state = yield from TestState("sim", simulator, dut, code)
 162
 163     sim.add_process(process)
 164     with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 165                        traces=[]):
 166         sim.run()
 167
 168     return simulator
 169
 170