src/openpower/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 import inspect
   7 import functools
   8 import types
   9
  10 from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict
  11 from openpower.util import fast_reg_to_spr, slow_reg_to_spr  # HACK!
  12 from openpower.consts import XERRegsEnum
  13
  14
  15 # TODO: make this a util routine (somewhere)
  16 def mask_extend(x, nbits, repeat):
  17     res = 0
  18     extended = (1<<repeat)-1
  19     for i in range(nbits):
  20         if x & (1<<i):
  21             res |= extended << (i*repeat)
  22     return res
  23
  24
  25 class SkipCase(Exception):
  26     """Raise this exception to skip a test case.
  27
  28     Usually you'd use one of the skip_case* decorators.
  29
  30     For use with TestAccumulatorBase
  31     """
  32
  33
  34 def _id(obj):
  35     """identity function"""
  36     return obj
  37
  38
  39 def skip_case(reason):
  40     """
  41     Unconditionally skip a test case.
  42
  43     Use like:
  44         @skip_case("my reason for skipping")
  45         def case_abc(self):
  46             ...
  47     or:
  48         @skip_case
  49         def case_def(self):
  50             ...
  51
  52     For use with TestAccumulatorBase
  53     """
  54     def decorator(item):
  55         assert not isinstance(item, type), \
  56             "can't use skip_case to decorate types"
  57
  58         @functools.wraps(item)
  59         def wrapper(*args, **kwargs):
  60             raise SkipCase(reason)
  61         return wrapper
  62     if isinstance(reason, types.FunctionType):
  63         item = reason
  64         reason = ""
  65         return decorator(item)
  66     return decorator
  67
  68
  69 def skip_case_if(condition, reason):
  70     """
  71     Conditionally skip a test case.
  72
  73     Use like:
  74         @skip_case_if(should_i_skip(), "my reason for skipping")
  75         def case_abc(self):
  76             ...
  77
  78     For use with TestAccumulatorBase
  79     """
  80     if condition:
  81         return skip_case(reason)
  82     return _id
  83
  84
  85 class TestAccumulatorBase:
  86
  87     def __init__(self):
  88         self.test_data = []
  89         # automatically identifies anything starting with "case_" and
  90         # runs it.  very similar to unittest auto-identification except
  91         # we need a different system
  92         for n, v in self.__class__.__dict__.items():
  93             if n.startswith("case_") and callable(v):
  94                 try:
  95                     v(self)
  96                 except SkipCase as e:
  97                     # TODO(programmerjake): translate to final test sending
  98                     # skip signal to unittest. for now, just print the skipped
  99                     # reason and ignore
 100                     print(f"SKIPPED({n}):", str(e))
 101
 102     def add_case(self, prog, initial_regs=None, initial_sprs=None,
 103                  initial_cr=0, initial_msr=0,
 104                  initial_mem=None,
 105                  initial_svstate=0):
 106
 107         test_name = inspect.stack()[1][3]  # name of caller of this function
 108         tc = TestCase(prog, test_name,
 109                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
 110                       msr=initial_msr,
 111                       mem=initial_mem,
 112                       svstate=initial_svstate)
 113
 114         self.test_data.append(tc)
 115
 116
 117 class TestCase:
 118     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
 119                  msr=0,
 120                  do_sim=True,
 121                  extra_break_addr=None,
 122                  svstate=0):
 123
 124         self.program = program
 125         self.name = name
 126
 127         if regs is None:
 128             regs = [0] * 32
 129         if sprs is None:
 130             sprs = {}
 131         if mem is None:
 132             mem = {}
 133         self.regs = regs
 134         self.sprs = sprs
 135         self.cr = cr
 136         self.mem = mem
 137         self.msr = msr
 138         self.do_sim = do_sim
 139         self.extra_break_addr = extra_break_addr
 140         self.svstate = svstate
 141
 142
 143 class ALUHelpers:
 144
 145     def get_sim_fast_reg(res, sim, dec2, reg, name):
 146         spr_sel = fast_reg_to_spr(reg)
 147         spr_data = sim.spr[spr_sel].value
 148         res[name] = spr_data
 149
 150     def get_sim_cia(res, sim, dec2):
 151         res['cia'] = sim.pc.CIA.value
 152
 153     # use this *after* the simulation has run a step (it returns CIA)
 154     def get_sim_nia(res, sim, dec2):
 155         res['nia'] = sim.pc.CIA.value
 156
 157     def get_sim_msr(res, sim, dec2):
 158         res['msr'] = sim.msr.value
 159
 160     def get_sim_slow_spr1(res, sim, dec2):
 161         spr1_en = yield dec2.e.read_spr1.ok
 162         if spr1_en:
 163             spr1_sel = yield dec2.e.read_spr1.data
 164             spr1_sel = slow_reg_to_spr(spr1_sel)
 165             spr1_data = sim.spr[spr1_sel].value
 166             res['spr1'] = spr1_data
 167
 168     def get_sim_fast_spr1(res, sim, dec2):
 169         fast1_en = yield dec2.e.read_fast1.ok
 170         if fast1_en:
 171             fast1_sel = yield dec2.e.read_fast1.data
 172             spr1_sel = fast_reg_to_spr(fast1_sel)
 173             spr1_data = sim.spr[spr1_sel].value
 174             res['fast1'] = spr1_data
 175
 176     def get_sim_fast_spr2(res, sim, dec2):
 177         fast2_en = yield dec2.e.read_fast2.ok
 178         if fast2_en:
 179             fast2_sel = yield dec2.e.read_fast2.data
 180             spr2_sel = fast_reg_to_spr(fast2_sel)
 181             spr2_data = sim.spr[spr2_sel].value
 182             res['fast2'] = spr2_data
 183
 184     def get_sim_fast_spr3(res, sim, dec2):
 185         fast3_en = yield dec2.e.read_fast3.ok
 186         if fast3_en:
 187             fast3_sel = yield dec2.e.read_fast3.data
 188             spr3_sel = fast_reg_to_spr(fast3_sel)
 189             spr3_data = sim.spr[spr3_sel].value
 190             res['fast3'] = spr3_data
 191
 192     def get_sim_cr_a(res, sim, dec2):
 193         cridx_ok = yield dec2.e.read_cr1.ok
 194         if cridx_ok:
 195             cridx = yield dec2.e.read_cr1.data
 196             res['cr_a'] = sim.crl[cridx].get_range().value
 197
 198     def get_sim_cr_b(res, sim, dec2):
 199         cridx_ok = yield dec2.e.read_cr2.ok
 200         if cridx_ok:
 201             cridx = yield dec2.e.read_cr2.data
 202             res['cr_b'] = sim.crl[cridx].get_range().value
 203
 204     def get_sim_cr_c(res, sim, dec2):
 205         cridx_ok = yield dec2.e.read_cr3.ok
 206         if cridx_ok:
 207             cridx = yield dec2.e.read_cr3.data
 208             res['cr_c'] = sim.crl[cridx].get_range().value
 209
 210     def get_sim_int_ra(res, sim, dec2):
 211         # TODO: immediate RA zero
 212         reg1_ok = yield dec2.e.read_reg1.ok
 213         if reg1_ok:
 214             data1 = yield dec2.e.read_reg1.data
 215             res['ra'] = sim.gpr(data1).value
 216
 217     def get_sim_int_rb(res, sim, dec2):
 218         reg2_ok = yield dec2.e.read_reg2.ok
 219         if reg2_ok:
 220             data = yield dec2.e.read_reg2.data
 221             res['rb'] = sim.gpr(data).value
 222
 223     def get_sim_int_rc(res, sim, dec2):
 224         reg3_ok = yield dec2.e.read_reg3.ok
 225         if reg3_ok:
 226             data = yield dec2.e.read_reg3.data
 227             res['rc'] = sim.gpr(data).value
 228
 229     def get_rd_sim_xer_ca(res, sim, dec2):
 230         cry_in = yield dec2.e.do.input_carry
 231         xer_in = yield dec2.e.xer_in
 232         if (xer_in & (1<<XERRegsEnum.CA)) or cry_in == CryIn.CA.value:
 233             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 234             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 235             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 236
 237     def set_int_ra(alu, dec2, inp):
 238         # TODO: immediate RA zero.
 239         if 'ra' in inp:
 240             yield alu.p.data_i.ra.eq(inp['ra'])
 241         else:
 242             yield alu.p.data_i.ra.eq(0)
 243
 244     def set_int_rb(alu, dec2, inp):
 245         yield alu.p.data_i.rb.eq(0)
 246         if 'rb' in inp:
 247             yield alu.p.data_i.rb.eq(inp['rb'])
 248         if not hasattr(dec2.e.do, "imm_data"):
 249             return
 250         # If there's an immediate, set the B operand to that
 251         imm_ok = yield dec2.e.do.imm_data.ok
 252         if imm_ok:
 253             data2 = yield dec2.e.do.imm_data.data
 254             yield alu.p.data_i.rb.eq(data2)
 255
 256     def set_int_rc(alu, dec2, inp):
 257         if 'rc' in inp:
 258             yield alu.p.data_i.rc.eq(inp['rc'])
 259         else:
 260             yield alu.p.data_i.rc.eq(0)
 261
 262     def set_xer_ca(alu, dec2, inp):
 263         if 'xer_ca' in inp:
 264             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 265             print("extra inputs: CA/32", bin(inp['xer_ca']))
 266
 267     def set_xer_ov(alu, dec2, inp):
 268         if 'xer_ov' in inp:
 269             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 270             print("extra inputs: OV/32", bin(inp['xer_ov']))
 271
 272     def set_xer_so(alu, dec2, inp):
 273         if 'xer_so' in inp:
 274             so = inp['xer_so']
 275             print("extra inputs: so", so)
 276             yield alu.p.data_i.xer_so.eq(so)
 277
 278     def set_msr(alu, dec2, inp):
 279         print("TODO: deprecate set_msr")
 280         if 'msr' in inp:
 281             yield alu.p.data_i.msr.eq(inp['msr'])
 282
 283     def set_cia(alu, dec2, inp):
 284         print("TODO: deprecate set_cia")
 285         if 'cia' in inp:
 286             yield alu.p.data_i.cia.eq(inp['cia'])
 287
 288     def set_slow_spr1(alu, dec2, inp):
 289         if 'spr1' in inp:
 290             yield alu.p.data_i.spr1.eq(inp['spr1'])
 291
 292     def set_slow_spr2(alu, dec2, inp):
 293         if 'spr2' in inp:
 294             yield alu.p.data_i.spr2.eq(inp['spr2'])
 295
 296     def set_fast_spr1(alu, dec2, inp):
 297         if 'fast1' in inp:
 298             yield alu.p.data_i.fast1.eq(inp['fast1'])
 299
 300     def set_fast_spr2(alu, dec2, inp):
 301         if 'fast2' in inp:
 302             yield alu.p.data_i.fast2.eq(inp['fast2'])
 303
 304     def set_fast_spr3(alu, dec2, inp):
 305         if 'fast3' in inp:
 306             yield alu.p.data_i.fast3.eq(inp['fast3'])
 307
 308     def set_cr_a(alu, dec2, inp):
 309         if 'cr_a' in inp:
 310             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 311
 312     def set_cr_b(alu, dec2, inp):
 313         if 'cr_b' in inp:
 314             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 315
 316     def set_cr_c(alu, dec2, inp):
 317         if 'cr_c' in inp:
 318             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 319
 320     def set_full_cr(alu, dec2, inp):
 321         if 'full_cr' in inp:
 322             full_reg = yield dec2.dec_cr_in.whole_reg.data
 323             full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok
 324             full_cr_mask = mask_extend(full_reg, 8, 4)
 325             yield alu.p.data_i.full_cr.eq(inp['full_cr'] & full_cr_mask)
 326         else:
 327             yield alu.p.data_i.full_cr.eq(0)
 328
 329     def get_slow_spr1(res, alu, dec2):
 330         spr1_valid = yield alu.n.data_o.spr1.ok
 331         if spr1_valid:
 332             res['spr1'] = yield alu.n.data_o.spr1.data
 333
 334     def get_slow_spr2(res, alu, dec2):
 335         spr2_valid = yield alu.n.data_o.spr2.ok
 336         if spr2_valid:
 337             res['spr2'] = yield alu.n.data_o.spr2.data
 338
 339     def get_fast_spr1(res, alu, dec2):
 340         spr1_valid = yield alu.n.data_o.fast1.ok
 341         if spr1_valid:
 342             res['fast1'] = yield alu.n.data_o.fast1.data
 343
 344     def get_fast_spr2(res, alu, dec2):
 345         spr2_valid = yield alu.n.data_o.fast2.ok
 346         if spr2_valid:
 347             res['fast2'] = yield alu.n.data_o.fast2.data
 348
 349     def get_cia(res, alu, dec2):
 350         res['cia'] = yield alu.p.data_i.cia
 351
 352     def get_nia(res, alu, dec2):
 353         nia_valid = yield alu.n.data_o.nia.ok
 354         if nia_valid:
 355             res['nia'] = yield alu.n.data_o.nia.data
 356
 357     def get_msr(res, alu, dec2):
 358         msr_valid = yield alu.n.data_o.msr.ok
 359         if msr_valid:
 360             res['msr'] = yield alu.n.data_o.msr.data
 361
 362     def get_int_o1(res, alu, dec2):
 363         out_reg_valid = yield dec2.e.write_ea.ok
 364         if out_reg_valid:
 365             res['o1'] = yield alu.n.data_o.o1.data
 366
 367     def get_int_o(res, alu, dec2):
 368         out_reg_valid = yield dec2.e.write_reg.ok
 369         if out_reg_valid:
 370             res['o'] = yield alu.n.data_o.o.data
 371
 372     def get_cr_a(res, alu, dec2):
 373         cridx_ok = yield dec2.e.write_cr.ok
 374         if cridx_ok:
 375             res['cr_a'] = yield alu.n.data_o.cr0.data
 376
 377     def get_xer_so(res, alu, dec2):
 378         oe = yield dec2.e.do.oe.oe
 379         oe_ok = yield dec2.e.do.oe.ok
 380         xer_out = yield dec2.e.xer_out
 381         if not (yield alu.n.data_o.xer_so.ok):
 382             return
 383         if xer_out or (oe and oe_ok):
 384             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 385
 386     def get_xer_ov(res, alu, dec2):
 387         oe = yield dec2.e.do.oe.oe
 388         oe_ok = yield dec2.e.do.oe.ok
 389         xer_out = yield dec2.e.xer_out
 390         if not (yield alu.n.data_o.xer_ov.ok):
 391             return
 392         if xer_out or (oe and oe_ok):
 393             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 394
 395     def get_xer_ca(res, alu, dec2):
 396         cry_out = yield dec2.e.do.output_carry
 397         xer_out = yield dec2.e.xer_out
 398         if not (yield alu.n.data_o.xer_ca.ok):
 399             return
 400         if xer_out or (cry_out):
 401             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 402
 403     def get_sim_int_o(res, sim, dec2):
 404         out_reg_valid = yield dec2.e.write_reg.ok
 405         if out_reg_valid:
 406             write_reg_idx = yield dec2.e.write_reg.data
 407             res['o'] = sim.gpr(write_reg_idx).value
 408
 409     def get_sim_int_o1(res, sim, dec2):
 410         out_reg_valid = yield dec2.e.write_ea.ok
 411         if out_reg_valid:
 412             write_reg_idx = yield dec2.e.write_ea.data
 413             res['o1'] = sim.gpr(write_reg_idx).value
 414
 415     def get_wr_sim_cr_a(res, sim, dec2):
 416         cridx_ok = yield dec2.e.write_cr.ok
 417         if cridx_ok:
 418             cridx = yield dec2.e.write_cr.data
 419             res['cr_a'] = sim.crl[cridx].get_range().value
 420
 421     def get_wr_fast_spr2(res, sim, dec2):
 422         ok = yield dec2.e.write_fast2.ok
 423         if ok:
 424             spr_num = yield dec2.e.write_fast2.data
 425             spr_num = fast_reg_to_spr(spr_num)
 426             spr_name = spr_dict[spr_num].SPR
 427             res['fast2'] = sim.spr[spr_name].value
 428
 429     def get_wr_fast_spr1(res, sim, dec2):
 430         ok = yield dec2.e.write_fast1.ok
 431         if ok:
 432             spr_num = yield dec2.e.write_fast1.data
 433             spr_num = fast_reg_to_spr(spr_num)
 434             spr_name = spr_dict[spr_num].SPR
 435             res['fast1'] = sim.spr[spr_name].value
 436
 437     def get_wr_slow_spr1(res, sim, dec2):
 438         ok = yield dec2.e.write_spr.ok
 439         if ok:
 440             spr_num = yield dec2.e.write_spr.data
 441             spr_num = slow_reg_to_spr(spr_num)
 442             spr_name = spr_dict[spr_num].SPR
 443             res['spr1'] = sim.spr[spr_name].value
 444
 445     def get_wr_sim_xer_ca(res, sim, dec2):
 446         # if not (yield alu.n.data_o.xer_ca.ok):
 447         #    return
 448         cry_out = yield dec2.e.do.output_carry
 449         xer_out = yield dec2.e.xer_out
 450         if cry_out or xer_out:
 451             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 452             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 453             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 454
 455     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 456         oe = yield dec2.e.do.oe.oe
 457         oe_ok = yield dec2.e.do.oe.ok
 458         xer_out = yield dec2.e.xer_out
 459         print("get_wr_sim_xer_ov", xer_out)
 460         if not (yield alu.n.data_o.xer_ov.ok):
 461             return
 462         if xer_out or (oe and oe_ok):
 463             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 464             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 465             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 466
 467     def get_wr_sim_xer_so(res, sim, alu, dec2):
 468         oe = yield dec2.e.do.oe.oe
 469         oe_ok = yield dec2.e.do.oe.ok
 470         xer_out = yield dec2.e.xer_out
 471         if not (yield alu.n.data_o.xer_so.ok):
 472             return
 473         if xer_out or (oe and oe_ok):
 474             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 475
 476     def get_sim_xer_ov(res, sim, dec2):
 477         oe = yield dec2.e.do.oe.oe
 478         oe_ok = yield dec2.e.do.oe.ok
 479         xer_in = yield dec2.e.xer_in
 480         print("get_sim_xer_ov", xer_in)
 481         if (xer_in & (1<<XERRegsEnum.OV)) or (oe and oe_ok):
 482             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 483             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 484             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 485
 486     def get_sim_xer_so(res, sim, dec2):
 487         print ("XER", sim.spr.__class__, sim.spr, sim.spr['XER'])
 488         oe = yield dec2.e.do.oe.oe
 489         oe_ok = yield dec2.e.do.oe.ok
 490         xer_in = yield dec2.e.xer_in
 491         rc = yield dec2.e.do.rc.rc
 492         rc_ok = yield dec2.e.do.rc.ok
 493         if (xer_in & (1<<XERRegsEnum.SO)) or (oe and oe_ok) or (rc and rc_ok):
 494             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 495
 496     def check_slow_spr1(dut, res, sim_o, msg):
 497         if 'spr1' in res:
 498             expected = sim_o['spr1']
 499             alu_out = res['spr1']
 500             print(f"expected {expected:x}, actual: {alu_out:x}")
 501             dut.assertEqual(expected, alu_out, msg)
 502
 503     def check_fast_spr1(dut, res, sim_o, msg):
 504         if 'fast1' in res:
 505             expected = sim_o['fast1']
 506             alu_out = res['fast1']
 507             print(f"expected {expected:x}, actual: {alu_out:x}")
 508             dut.assertEqual(expected, alu_out, msg)
 509
 510     def check_fast_spr2(dut, res, sim_o, msg):
 511         if 'fast2' in res:
 512             expected = sim_o['fast2']
 513             alu_out = res['fast2']
 514             print(f"expected {expected:x}, actual: {alu_out:x}")
 515             dut.assertEqual(expected, alu_out, msg)
 516
 517     def check_int_o1(dut, res, sim_o, msg):
 518         if 'o1' in res:
 519             expected = sim_o['o1']
 520             alu_out = res['o1']
 521             print(f"expected {expected:x}, actual: {alu_out:x}")
 522             dut.assertEqual(expected, alu_out, msg)
 523
 524     def check_int_o(dut, res, sim_o, msg):
 525         if 'o' in res:
 526             expected = sim_o['o']
 527             alu_out = res['o']
 528             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 529             dut.assertEqual(expected, alu_out, msg)
 530
 531     def check_msr(dut, res, sim_o, msg):
 532         if 'msr' in res:
 533             expected = sim_o['msr']
 534             alu_out = res['msr']
 535             print(f"expected {expected:x}, actual: {alu_out:x}")
 536             dut.assertEqual(expected, alu_out, msg)
 537
 538     def check_nia(dut, res, sim_o, msg):
 539         if 'nia' in res:
 540             expected = sim_o['nia']
 541             alu_out = res['nia']
 542             print(f"expected {expected:x}, actual: {alu_out:x}")
 543             dut.assertEqual(expected, alu_out, msg)
 544
 545     def check_cr_a(dut, res, sim_o, msg):
 546         if 'cr_a' in res:
 547             cr_expected = sim_o['cr_a']
 548             cr_actual = res['cr_a']
 549             print("CR", cr_expected, cr_actual)
 550             dut.assertEqual(cr_expected, cr_actual, msg)
 551
 552     def check_xer_ca(dut, res, sim_o, msg):
 553         if 'xer_ca' in res:
 554             ca_expected = sim_o['xer_ca']
 555             ca_actual = res['xer_ca']
 556             print("CA", ca_expected, ca_actual)
 557             dut.assertEqual(ca_expected, ca_actual, msg)
 558
 559     def check_xer_ov(dut, res, sim_o, msg):
 560         if 'xer_ov' in res:
 561             ov_expected = sim_o['xer_ov']
 562             ov_actual = res['xer_ov']
 563             print("OV", ov_expected, ov_actual)
 564             dut.assertEqual(ov_expected, ov_actual, msg)
 565
 566     def check_xer_so(dut, res, sim_o, msg):
 567         if 'xer_so' in res:
 568             so_expected = sim_o['xer_so']
 569             so_actual = res['xer_so']
 570             print("SO", so_expected, so_actual)
 571             dut.assertEqual(so_expected, so_actual, msg)