src/openpower/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from contextlib import contextmanager
   7 import sys
   8 import functools
   9 import types
  10 import os
  11
  12 from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict
  13 from openpower.util import LogKind, log, \
  14     fast_reg_to_spr, slow_reg_to_spr  # HACK!
  15 from openpower.consts import XERRegsEnum, DEFAULT_MSR
  16
  17
  18 # TODO: make this a util routine (somewhere)
  19 def mask_extend(x, nbits, repeat):
  20     res = 0
  21     extended = (1<<repeat)-1
  22     for i in range(nbits):
  23         if x & (1<<i):
  24             res |= extended << (i*repeat)
  25     return res
  26
  27
  28 class SkipCase(Exception):
  29     """Raise this exception to skip a test case.
  30
  31     Usually you'd use one of the skip_case* decorators.
  32
  33     For use with TestAccumulatorBase
  34     """
  35
  36
  37 def _id(obj):
  38     """identity function"""
  39     return obj
  40
  41
  42 def skip_case(reason):
  43     """
  44     Unconditionally skip a test case.
  45
  46     Use like:
  47         @skip_case("my reason for skipping")
  48         def case_abc(self):
  49             ...
  50     or:
  51         @skip_case
  52         def case_def(self):
  53             ...
  54
  55     For use with TestAccumulatorBase
  56     """
  57     def decorator(item):
  58         assert not isinstance(item, type), \
  59             "can't use skip_case to decorate types"
  60
  61         @functools.wraps(item)
  62         def wrapper(*args, **kwargs):
  63             raise SkipCase(reason)
  64         return wrapper
  65     if isinstance(reason, types.FunctionType):
  66         item = reason
  67         reason = ""
  68         return decorator(item)
  69     return decorator
  70
  71
  72 def skip_case_if(condition, reason):
  73     """
  74     Conditionally skip a test case.
  75
  76     Use like:
  77         @skip_case_if(should_i_skip(), "my reason for skipping")
  78         def case_abc(self):
  79             ...
  80
  81     For use with TestAccumulatorBase
  82     """
  83     if condition:
  84         return skip_case(reason)
  85     return _id
  86
  87
  88 class TestAccumulatorBase:
  89     __test__ = False  # pytest should ignore this class
  90
  91     def __init__(self):
  92         self.__subtest_args = {}
  93
  94         self.test_data = []
  95         # automatically identifies anything starting with "case_" and
  96         # runs it.  very similar to unittest auto-identification except
  97         # we need a different system
  98         for n, v in self.__class__.__dict__.items():
  99             if n.startswith("case_") and callable(v):
 100                 try:
 101                     v(self)
 102                 except SkipCase as e:
 103                     # TODO(programmerjake): translate to final test sending
 104                     # skip signal to unittest. for now, just print the skipped
 105                     # reason and ignore
 106                     log(f"SKIPPED({n}):", str(e), kind=LogKind.SkipCase)
 107
 108     @contextmanager
 109     def subTest(self, **kwargs):
 110         old_subtest_args = self.__subtest_args
 111         try:
 112             self.__subtest_args = old_subtest_args.copy()
 113             self.__subtest_args.update(**kwargs)
 114             yield
 115         finally:
 116             self.__subtest_args = old_subtest_args
 117
 118     def add_case(self, prog, initial_regs=None, initial_sprs=None,
 119                  initial_cr=0, initial_msr=DEFAULT_MSR,
 120                  initial_mem=None,
 121                  initial_svstate=0,
 122                  expected=None,
 123                  stop_at_pc=None,
 124                  fpregs=None,
 125                  initial_fpscr=None,
 126                  src_loc_at=0):
 127
 128         c = sys._getframe(1 + src_loc_at).f_code
 129         # name of caller of this function
 130         test_name = c.co_name
 131         # name of file containing test case
 132         test_file = os.path.splitext(os.path.basename(c.co_filename))[0]
 133         tc = TestCase(prog, test_name,
 134                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
 135                       msr=initial_msr,
 136                       mem=initial_mem,
 137                       svstate=initial_svstate,
 138                       expected=expected,
 139                       stop_at_pc=stop_at_pc,
 140                       test_file=test_file,
 141                       subtest_args=self.__subtest_args.copy(),
 142                       fpregs=fpregs,
 143                       initial_fpscr=initial_fpscr)
 144
 145         self.test_data.append(tc)
 146
 147
 148 class TestCase:
 149     __test__ = False  # pytest should ignore this class
 150
 151     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
 152                  msr=0,
 153                  do_sim=True,
 154                  extra_break_addr=None,
 155                  svstate=0,
 156                  expected=None,
 157                  stop_at_pc=None,
 158                  test_file=None,
 159                  subtest_args=None,
 160                  fpregs=None,
 161                  initial_fpscr=None):
 162
 163         self.program = program
 164         self.name = name
 165
 166         if regs is None:
 167             regs = [0] * 32
 168         if sprs is None:
 169             sprs = {}
 170         if mem is None:
 171             mem = {}
 172         if fpregs is None:
 173             fpregs = [0] * 32
 174         self.regs = regs
 175         self.fpregs = fpregs
 176         self.sprs = sprs
 177         self.cr = cr
 178         self.mem = mem
 179         self.msr = msr
 180         self.do_sim = do_sim
 181         self.extra_break_addr = extra_break_addr
 182         self.svstate = svstate
 183         self.expected = expected # expected results from the test
 184         self.stop_at_pc = stop_at_pc # hard-stop address (do not attempt to run)
 185         self.test_file = test_file
 186         self.subtest_args = {} if subtest_args is None else dict(subtest_args)
 187         if initial_fpscr is None:
 188             initial_fpscr = 0
 189         self.initial_fpscr = initial_fpscr
 190
 191
 192 class ALUHelpers:
 193
 194     def get_sim_fast_reg(res, sim, dec2, reg, name):
 195         spr_sel = fast_reg_to_spr(reg)
 196         spr_data = sim.spr[spr_sel].value
 197         res[name] = spr_data
 198
 199     def get_sim_cia(res, sim, dec2):
 200         res['cia'] = sim.pc.CIA.value
 201
 202     # use this *after* the simulation has run a step (it returns CIA)
 203     def get_sim_nia(res, sim, dec2):
 204         res['nia'] = sim.pc.CIA.value
 205
 206     def get_sim_msr(res, sim, dec2):
 207         res['msr'] = sim.msr.value
 208
 209     def get_sim_slow_spr1(res, sim, dec2):
 210         spr1_en = yield dec2.e.read_spr1.ok
 211         if spr1_en:
 212             spr1_sel = yield dec2.e.read_spr1.data
 213             spr1_sel = slow_reg_to_spr(spr1_sel)
 214             spr1_data = sim.spr[spr1_sel].value
 215             res['spr1'] = spr1_data
 216
 217     def get_sim_fast_spr1(res, sim, dec2):
 218         fast1_en = yield dec2.e.read_fast1.ok
 219         if fast1_en:
 220             fast1_sel = yield dec2.e.read_fast1.data
 221             spr1_sel = fast_reg_to_spr(fast1_sel)
 222             spr1_data = sim.spr[spr1_sel].value
 223             res['fast1'] = spr1_data
 224
 225     def get_sim_fast_spr2(res, sim, dec2):
 226         fast2_en = yield dec2.e.read_fast2.ok
 227         if fast2_en:
 228             fast2_sel = yield dec2.e.read_fast2.data
 229             spr2_sel = fast_reg_to_spr(fast2_sel)
 230             spr2_data = sim.spr[spr2_sel].value
 231             res['fast2'] = spr2_data
 232
 233     def get_sim_fast_spr3(res, sim, dec2):
 234         fast3_en = yield dec2.e.read_fast3.ok
 235         if fast3_en:
 236             fast3_sel = yield dec2.e.read_fast3.data
 237             spr3_sel = fast_reg_to_spr(fast3_sel)
 238             spr3_data = sim.spr[spr3_sel].value
 239             res['fast3'] = spr3_data
 240
 241     def get_sim_cr_a(res, sim, dec2):
 242         cridx_ok = yield dec2.e.read_cr1.ok
 243         if cridx_ok:
 244             cridx = yield dec2.e.read_cr1.data
 245             res['cr_a'] = sim.crl[cridx].get_range().value
 246
 247     def get_sim_cr_b(res, sim, dec2):
 248         cridx_ok = yield dec2.e.read_cr2.ok
 249         if cridx_ok:
 250             cridx = yield dec2.e.read_cr2.data
 251             res['cr_b'] = sim.crl[cridx].get_range().value
 252
 253     def get_sim_cr_c(res, sim, dec2):
 254         cridx_ok = yield dec2.e.read_cr3.ok
 255         if cridx_ok:
 256             cridx = yield dec2.e.read_cr3.data
 257             res['cr_c'] = sim.crl[cridx].get_range().value
 258
 259     def get_sim_int_ra(res, sim, dec2):
 260         # TODO: immediate RA zero
 261         reg1_ok = yield dec2.e.read_reg1.ok
 262         if reg1_ok:
 263             data1 = yield dec2.e.read_reg1.data
 264             res['ra'] = sim.gpr(data1).value
 265
 266     def get_sim_int_rb(res, sim, dec2):
 267         reg2_ok = yield dec2.e.read_reg2.ok
 268         if reg2_ok:
 269             data = yield dec2.e.read_reg2.data
 270             res['rb'] = sim.gpr(data).value
 271
 272     def get_sim_int_rc(res, sim, dec2):
 273         reg3_ok = yield dec2.e.read_reg3.ok
 274         if reg3_ok:
 275             data = yield dec2.e.read_reg3.data
 276             res['rc'] = sim.gpr(data).value
 277
 278     def get_rd_sim_xer_ca(res, sim, dec2):
 279         cry_in = yield dec2.e.do.input_carry
 280         xer_in = yield dec2.e.xer_in
 281         if (xer_in & (1<<XERRegsEnum.CA)) or cry_in == CryIn.CA.value:
 282             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 283             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 284             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 285
 286     def set_int_ra(alu, dec2, inp):
 287         # TODO: immediate RA zero.
 288         if 'ra' in inp:
 289             yield alu.p.i_data.ra.eq(inp['ra'])
 290         else:
 291             yield alu.p.i_data.ra.eq(0)
 292
 293     def set_int_rb(alu, dec2, inp):
 294         yield alu.p.i_data.rb.eq(0)
 295         if 'rb' in inp:
 296             yield alu.p.i_data.rb.eq(inp['rb'])
 297         if not hasattr(dec2.e.do, "imm_data"):
 298             return
 299         # If there's an immediate, set the B operand to that
 300         imm_ok = yield dec2.e.do.imm_data.ok
 301         if imm_ok:
 302             data2 = yield dec2.e.do.imm_data.data
 303             yield alu.p.i_data.rb.eq(data2)
 304
 305     def set_int_rc(alu, dec2, inp):
 306         if 'rc' in inp:
 307             yield alu.p.i_data.rc.eq(inp['rc'])
 308         else:
 309             yield alu.p.i_data.rc.eq(0)
 310
 311     def set_xer_ca(alu, dec2, inp):
 312         if 'xer_ca' in inp:
 313             yield alu.p.i_data.xer_ca.eq(inp['xer_ca'])
 314             print("extra inputs: CA/32", bin(inp['xer_ca']))
 315
 316     def set_xer_ov(alu, dec2, inp):
 317         if 'xer_ov' in inp:
 318             yield alu.p.i_data.xer_ov.eq(inp['xer_ov'])
 319             print("extra inputs: OV/32", bin(inp['xer_ov']))
 320
 321     def set_xer_so(alu, dec2, inp):
 322         if 'xer_so' in inp:
 323             so = inp['xer_so']
 324             print("extra inputs: so", so)
 325             yield alu.p.i_data.xer_so.eq(so)
 326
 327     def set_msr(alu, dec2, inp):
 328         print("TODO: deprecate set_msr")
 329         if 'msr' in inp:
 330             yield alu.p.i_data.msr.eq(inp['msr'])
 331
 332     def set_cia(alu, dec2, inp):
 333         print("TODO: deprecate set_cia")
 334         if 'cia' in inp:
 335             yield alu.p.i_data.cia.eq(inp['cia'])
 336
 337     def set_slow_spr1(alu, dec2, inp):
 338         if 'spr1' in inp:
 339             yield alu.p.i_data.spr1.eq(inp['spr1'])
 340
 341     def set_slow_spr2(alu, dec2, inp):
 342         if 'spr2' in inp:
 343             yield alu.p.i_data.spr2.eq(inp['spr2'])
 344
 345     def set_fast_spr1(alu, dec2, inp):
 346         if 'fast1' in inp:
 347             yield alu.p.i_data.fast1.eq(inp['fast1'])
 348
 349     def set_fast_spr2(alu, dec2, inp):
 350         if 'fast2' in inp:
 351             yield alu.p.i_data.fast2.eq(inp['fast2'])
 352
 353     def set_fast_spr3(alu, dec2, inp):
 354         if 'fast3' in inp:
 355             yield alu.p.i_data.fast3.eq(inp['fast3'])
 356
 357     def set_cr_a(alu, dec2, inp):
 358         if 'cr_a' in inp:
 359             yield alu.p.i_data.cr_a.eq(inp['cr_a'])
 360
 361     def set_cr_b(alu, dec2, inp):
 362         if 'cr_b' in inp:
 363             yield alu.p.i_data.cr_b.eq(inp['cr_b'])
 364
 365     def set_cr_c(alu, dec2, inp):
 366         if 'cr_c' in inp:
 367             yield alu.p.i_data.cr_c.eq(inp['cr_c'])
 368
 369     def set_full_cr(alu, dec2, inp):
 370         if 'full_cr' in inp:
 371             full_reg = yield dec2.dec_cr_in.whole_reg.data
 372             full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok
 373             full_cr_mask = mask_extend(full_reg, 8, 4)
 374             yield alu.p.i_data.full_cr.eq(inp['full_cr'] & full_cr_mask)
 375         else:
 376             yield alu.p.i_data.full_cr.eq(0)
 377
 378     def get_slow_spr1(res, alu, dec2):
 379         spr1_valid = yield alu.n.o_data.spr1.ok
 380         if spr1_valid:
 381             res['spr1'] = yield alu.n.o_data.spr1.data
 382
 383     def get_slow_spr2(res, alu, dec2):
 384         spr2_valid = yield alu.n.o_data.spr2.ok
 385         if spr2_valid:
 386             res['spr2'] = yield alu.n.o_data.spr2.data
 387
 388     def get_fast_spr1(res, alu, dec2):
 389         spr1_valid = yield alu.n.o_data.fast1.ok
 390         if spr1_valid:
 391             res['fast1'] = yield alu.n.o_data.fast1.data
 392
 393     def get_fast_spr2(res, alu, dec2):
 394         spr2_valid = yield alu.n.o_data.fast2.ok
 395         if spr2_valid:
 396             res['fast2'] = yield alu.n.o_data.fast2.data
 397
 398     def get_fast_spr3(res, alu, dec2):
 399         spr3_valid = yield alu.n.o_data.fast3.ok
 400         if spr3_valid:
 401             res['fast3'] = yield alu.n.o_data.fast3.data
 402
 403     def get_cia(res, alu, dec2):
 404         res['cia'] = yield alu.p.i_data.cia
 405
 406     def get_nia(res, alu, dec2):
 407         nia_valid = yield alu.n.o_data.nia.ok
 408         if nia_valid:
 409             res['nia'] = yield alu.n.o_data.nia.data
 410
 411     def get_msr(res, alu, dec2):
 412         msr_valid = yield alu.n.o_data.msr.ok
 413         if msr_valid:
 414             res['msr'] = yield alu.n.o_data.msr.data
 415
 416     def get_int_o1(res, alu, dec2):
 417         out_reg_valid = yield dec2.e.write_ea.ok
 418         if out_reg_valid:
 419             res['o1'] = yield alu.n.o_data.o1.data
 420
 421     def get_int_o(res, alu, dec2):
 422         out_reg_valid = yield dec2.e.write_reg.ok
 423         if out_reg_valid:
 424             res['o'] = yield alu.n.o_data.o.data
 425
 426     def get_cr_a(res, alu, dec2):
 427         cridx_ok = yield dec2.e.write_cr.ok
 428         if cridx_ok:
 429             res['cr_a'] = yield alu.n.o_data.cr0.data
 430
 431     def get_xer_so(res, alu, dec2):
 432         oe = yield dec2.e.do.oe.oe
 433         oe_ok = yield dec2.e.do.oe.ok
 434         xer_out = yield dec2.e.xer_out
 435         if not (yield alu.n.o_data.xer_so.ok):
 436             return
 437         if xer_out or (oe and oe_ok):
 438             res['xer_so'] = yield alu.n.o_data.xer_so.data[0]
 439
 440     def get_xer_ov(res, alu, dec2):
 441         oe = yield dec2.e.do.oe.oe
 442         oe_ok = yield dec2.e.do.oe.ok
 443         xer_out = yield dec2.e.xer_out
 444         if not (yield alu.n.o_data.xer_ov.ok):
 445             return
 446         if xer_out or (oe and oe_ok):
 447             res['xer_ov'] = yield alu.n.o_data.xer_ov.data
 448
 449     def get_xer_ca(res, alu, dec2):
 450         cry_out = yield dec2.e.do.output_carry
 451         xer_out = yield dec2.e.xer_out
 452         if not (yield alu.n.o_data.xer_ca.ok):
 453             return
 454         if xer_out or (cry_out):
 455             res['xer_ca'] = yield alu.n.o_data.xer_ca.data
 456
 457     def get_sim_int_o(res, sim, dec2):
 458         out_reg_valid = yield dec2.e.write_reg.ok
 459         if out_reg_valid:
 460             write_reg_idx = yield dec2.e.write_reg.data
 461             res['o'] = sim.gpr(write_reg_idx).value
 462
 463     def get_sim_int_o1(res, sim, dec2):
 464         out_reg_valid = yield dec2.e.write_ea.ok
 465         if out_reg_valid:
 466             write_reg_idx = yield dec2.e.write_ea.data
 467             res['o1'] = sim.gpr(write_reg_idx).value
 468
 469     def get_wr_sim_cr_a(res, sim, dec2):
 470         cridx_ok = yield dec2.e.write_cr.ok
 471         if cridx_ok:
 472             cridx = yield dec2.e.write_cr.data
 473             res['cr_a'] = sim.crl[cridx].get_range().value
 474
 475     def get_wr_fast_spr3(res, sim, dec2):
 476         ok = yield dec2.e.write_fast3.ok
 477         if ok:
 478             spr_num = yield dec2.e.write_fast3.data
 479             spr_num = fast_reg_to_spr(spr_num)
 480             spr_name = spr_dict[spr_num].SPR
 481             res['fast3'] = sim.spr[spr_name].value
 482
 483     def get_wr_fast_spr2(res, sim, dec2):
 484         ok = yield dec2.e.write_fast2.ok
 485         if ok:
 486             spr_num = yield dec2.e.write_fast2.data
 487             spr_num = fast_reg_to_spr(spr_num)
 488             spr_name = spr_dict[spr_num].SPR
 489             res['fast2'] = sim.spr[spr_name].value
 490
 491     def get_wr_fast_spr1(res, sim, dec2):
 492         ok = yield dec2.e.write_fast1.ok
 493         if ok:
 494             spr_num = yield dec2.e.write_fast1.data
 495             spr_num = fast_reg_to_spr(spr_num)
 496             spr_name = spr_dict[spr_num].SPR
 497             res['fast1'] = sim.spr[spr_name].value
 498
 499     def get_wr_slow_spr1(res, sim, dec2):
 500         ok = yield dec2.e.write_spr.ok
 501         if ok:
 502             spr_num = yield dec2.e.write_spr.data
 503             spr_num = slow_reg_to_spr(spr_num)
 504             spr_name = spr_dict[spr_num].SPR
 505             res['spr1'] = sim.spr[spr_name].value
 506
 507     def get_wr_sim_xer_ca(res, sim, dec2):
 508         # if not (yield alu.n.o_data.xer_ca.ok):
 509         #    return
 510         cry_out = yield dec2.e.do.output_carry
 511         xer_out = yield dec2.e.xer_out
 512         if cry_out or xer_out:
 513             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 514             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 515             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 516
 517     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 518         oe = yield dec2.e.do.oe.oe
 519         oe_ok = yield dec2.e.do.oe.ok
 520         xer_out = yield dec2.e.xer_out
 521         print("get_wr_sim_xer_ov", xer_out)
 522         if not (yield alu.n.o_data.xer_ov.ok):
 523             return
 524         if xer_out or (oe and oe_ok):
 525             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 526             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 527             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 528
 529     def get_wr_sim_xer_so(res, sim, alu, dec2):
 530         oe = yield dec2.e.do.oe.oe
 531         oe_ok = yield dec2.e.do.oe.ok
 532         xer_out = yield dec2.e.xer_out
 533         if not (yield alu.n.o_data.xer_so.ok):
 534             return
 535         if xer_out or (oe and oe_ok):
 536             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 537
 538     def get_sim_xer_ov(res, sim, dec2):
 539         oe = yield dec2.e.do.oe.oe
 540         oe_ok = yield dec2.e.do.oe.ok
 541         xer_in = yield dec2.e.xer_in
 542         print("get_sim_xer_ov", xer_in)
 543         if (xer_in & (1<<XERRegsEnum.OV)) or (oe and oe_ok):
 544             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 545             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 546             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 547
 548     def get_sim_xer_so(res, sim, dec2):
 549         print ("XER", sim.spr.__class__, sim.spr, sim.spr['XER'])
 550         oe = yield dec2.e.do.oe.oe
 551         oe_ok = yield dec2.e.do.oe.ok
 552         xer_in = yield dec2.e.xer_in
 553         rc = yield dec2.e.do.rc.rc
 554         rc_ok = yield dec2.e.do.rc.ok
 555         if (xer_in & (1<<XERRegsEnum.SO)) or (oe and oe_ok) or (rc and rc_ok):
 556             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 557
 558     def check_slow_spr1(dut, res, sim_o, msg):
 559         if 'spr1' in res:
 560             expected = sim_o['spr1']
 561             alu_out = res['spr1']
 562             print(f"expected {expected:x}, actual: {alu_out:x}")
 563             dut.assertEqual(expected, alu_out, msg)
 564
 565     def check_fast_spr1(dut, res, sim_o, msg):
 566         if 'fast1' in res:
 567             expected = sim_o['fast1']
 568             alu_out = res['fast1']
 569             print(f"expected {expected:x}, actual: {alu_out:x}")
 570             dut.assertEqual(expected, alu_out, msg)
 571
 572     def check_fast_spr2(dut, res, sim_o, msg):
 573         if 'fast2' in res:
 574             expected = sim_o['fast2']
 575             alu_out = res['fast2']
 576             print(f"expected {expected:x}, actual: {alu_out:x}")
 577             dut.assertEqual(expected, alu_out, msg)
 578
 579     def check_fast_spr3(dut, res, sim_o, msg):
 580         if 'fast3' in res:
 581             expected = sim_o['fast3']
 582             alu_out = res['fast3']
 583             print(f"expected {expected:x}, actual: {alu_out:x}")
 584             dut.assertEqual(expected, alu_out, msg)
 585
 586     def check_int_o1(dut, res, sim_o, msg):
 587         if 'o1' in res:
 588             expected = sim_o['o1']
 589             alu_out = res['o1']
 590             print(f"expected {expected:x}, actual: {alu_out:x}")
 591             dut.assertEqual(expected, alu_out, msg)
 592
 593     def check_int_o(dut, res, sim_o, msg):
 594         if 'o' in res:
 595             expected = sim_o['o']
 596             alu_out = res['o']
 597             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 598             dut.assertEqual(expected, alu_out, msg)
 599
 600     def check_msr(dut, res, sim_o, msg):
 601         if 'msr' in res:
 602             expected = sim_o['msr']
 603             alu_out = res['msr']
 604             print(f"expected {expected:x}, actual: {alu_out:x}")
 605             dut.assertEqual(expected, alu_out, msg)
 606
 607     def check_nia(dut, res, sim_o, msg):
 608         if 'nia' in res:
 609             expected = sim_o['nia']
 610             alu_out = res['nia']
 611             print(f"expected {expected:x}, actual: {alu_out:x}")
 612             dut.assertEqual(expected, alu_out, msg)
 613
 614     def check_cr_a(dut, res, sim_o, msg):
 615         if 'cr_a' in res:
 616             cr_expected = sim_o['cr_a']
 617             cr_actual = res['cr_a']
 618             print("CR", cr_expected, cr_actual)
 619             dut.assertEqual(cr_expected, cr_actual, msg)
 620
 621     def check_xer_ca(dut, res, sim_o, msg):
 622         if 'xer_ca' in res:
 623             ca_expected = sim_o['xer_ca']
 624             ca_actual = res['xer_ca']
 625             print("CA", ca_expected, ca_actual)
 626             dut.assertEqual(ca_expected, ca_actual, msg)
 627
 628     def check_xer_ov(dut, res, sim_o, msg):
 629         if 'xer_ov' in res:
 630             ov_expected = sim_o['xer_ov']
 631             ov_actual = res['xer_ov']
 632             print("OV", ov_expected, ov_actual)
 633             dut.assertEqual(ov_expected, ov_actual, msg)
 634
 635     def check_xer_so(dut, res, sim_o, msg):
 636         if 'xer_so' in res:
 637             so_expected = sim_o['xer_so']
 638             so_actual = res['xer_so']
 639             print("SO", so_expected, so_actual)
 640             dut.assertEqual(so_expected, so_actual, msg)