src/scoreboard/fn_unit.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Cat, Array, Const, Elaboratable
   4 from nmutil.latch import SRLatch
   5 from nmigen.lib.coding import Decoder
   6
   7 from .shadow_fn import ShadowFn
   8
   9
  10 class FnUnit(Elaboratable):
  11     """ implements 11.4.8 function unit, p31
  12         also implements optional shadowing 11.5.1, p55
  13
  14         shadowing can be used for branches as well as exceptions (interrupts),
  15         load/store hold (exceptions again), and vector-element predication
  16         (once the predicate is known, which it may not be at instruction issue)
  17
  18         Inputs
  19
  20         * :wid:         register file width
  21         * :shadow_wid:  number of shadow/fail/good/go_die sets
  22         * :n_dests:     number of destination regfile(s) (index: rfile_sel_i)
  23         * :wr_pend:     if true, writable observes the g_wr_pend_i vector
  24                         otherwise observes g_rd_pend_i
  25
  26         notes:
  27
  28         * dest_i / src1_i / src2_i are in *binary*, whereas...
  29         * ...g_rd_pend_i / g_wr_pend_i and rd_pend_o / wr_pend_o are UNARY
  30         * req_rel_i (request release) is the direct equivalent of pipeline
  31                     "output valid" (valid_o)
  32         * recover is a local python variable (actually go_die_o)
  33         * when shadow_wid = 0, recover and shadown are Consts (i.e. do nothing)
  34         * wr_pend is set False for the majority of uses: however for
  35           use in a STORE Function Unit it is set to True
  36     """
  37     def __init__(self, wid, shadow_wid=0, n_dests=1, wr_pend=False):
  38         self.reg_width = wid
  39         self.n_dests = n_dests
  40         self.shadow_wid = shadow_wid
  41         self.wr_pend = wr_pend
  42
  43         # inputs
  44         if n_dests > 1:
  45             self.rfile_sel_i = Signal(max=n_dests, reset_less=True)
  46         else:
  47             self.rfile_sel_i = Const(0) # no selection.  gets Array[0]
  48         self.dest_i = Signal(max=wid, reset_less=True) # Dest R# in (top)
  49         self.src1_i = Signal(max=wid, reset_less=True) # oper1 R# in (top)
  50         self.src2_i = Signal(max=wid, reset_less=True) # oper2 R# in (top)
  51         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  52
  53         self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
  54         self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
  55         self.req_rel_i = Signal(reset_less=True)  # request release (left)
  56
  57         self.g_xx_pend_i = Array(Signal(wid, reset_less=True, name="g_pend_i") \
  58                                for i in range(n_dests)) # global rd (right)
  59         self.g_wr_pend_i = Signal(wid, reset_less=True) # global wr (right)
  60
  61         if shadow_wid:
  62             self.shadow_i = Signal(shadow_wid, reset_less=True)
  63             self.s_fail_i  = Signal(shadow_wid, reset_less=True)
  64             self.s_good_i  = Signal(shadow_wid, reset_less=True)
  65             self.go_die_o  = Signal(reset_less=True)
  66
  67         # outputs
  68         self.readable_o = Signal(reset_less=True) # Readable out (right)
  69         self.writable_o = Array(Signal(reset_less=True, name="writable_o") \
  70                                for i in range(n_dests)) # writable out (right)
  71         self.busy_o = Signal(reset_less=True) # busy out (left)
  72
  73         self.src1_pend_o = Signal(wid, reset_less=True) # src1 pending
  74         self.src2_pend_o = Signal(wid, reset_less=True) # src1 pending
  75         self.rd_pend_o = Signal(wid, reset_less=True) # rd pending (right)
  76         self.xx_pend_o = Array(Signal(wid, reset_less=True, name="pend_o") \
  77                                for i in range(n_dests))# wr pending (right)
  78
  79     def elaborate(self, platform):
  80         m = Module()
  81         m.submodules.rd_l = rd_l = SRLatch(sync=False)
  82         m.submodules.wr_l = wr_l = SRLatch(sync=False)
  83         m.submodules.dest_d = dest_d = Decoder(self.reg_width)
  84         m.submodules.src1_d = src1_d = Decoder(self.reg_width)
  85         m.submodules.src2_d = src2_d = Decoder(self.reg_width)
  86         s_latches = []
  87         for i in range(self.shadow_wid):
  88             sh = ShadowFn()
  89             setattr(m.submodules, "shadow%d" % i, sh)
  90             s_latches.append(sh)
  91
  92         # shadow / recover (optional: shadow_wid > 0)
  93         if self.shadow_wid:
  94             recover = self.go_die_o
  95             shadown = Signal(reset_less=True)
  96             i_l = []
  97             fail_l = []
  98             good_l = []
  99             shi_l = []
 100             sho_l = []
 101             rec_l = []
 102             # get list of latch signals. really must be a better way to do this
 103             for l in s_latches:
 104                 i_l.append(l.issue_i)
 105                 shi_l.append(l.shadow_i)
 106                 fail_l.append(l.s_fail_i)
 107                 good_l.append(l.s_good_i)
 108                 sho_l.append(l.shadow_o)
 109                 rec_l.append(l.recover_o)
 110             m.d.comb += Cat(*i_l).eq(self.issue_i)
 111             m.d.comb += Cat(*fail_l).eq(self.s_fail_i)
 112             m.d.comb += Cat(*good_l).eq(self.s_good_i)
 113             m.d.comb += Cat(*shi_l).eq(self.shadow_i)
 114             m.d.comb += shadown.eq(~(Cat(*sho_l).bool()))
 115             m.d.comb += recover.eq(Cat(*rec_l).bool())
 116         else:
 117             shadown = Const(1)
 118             recover = Const(0)
 119
 120         # selector
 121         xx_pend_o = self.xx_pend_o[self.rfile_sel_i]
 122         writable_o = self.writable_o[self.rfile_sel_i]
 123         g_pend_i = self.g_xx_pend_i[self.rfile_sel_i]
 124
 125         for i in range(self.n_dests):
 126             m.d.comb += self.xx_pend_o[i].eq(0)  # initialise all array
 127             m.d.comb += self.writable_o[i].eq(0) # to zero
 128
 129         # go_wr latch: reset on go_wr HI, set on issue
 130         m.d.comb += wr_l.s.eq(self.issue_i)
 131         m.d.comb += wr_l.r.eq(self.go_wr_i | recover)
 132
 133         # src1 latch: reset on go_rd HI, set on issue
 134         m.d.comb += rd_l.s.eq(self.issue_i)
 135         m.d.comb += rd_l.r.eq(self.go_rd_i | recover)
 136
 137         # dest decoder: write-pending out
 138         m.d.comb += dest_d.i.eq(self.dest_i)
 139         m.d.comb += dest_d.n.eq(wr_l.qn) # decode is inverted
 140         m.d.comb += self.busy_o.eq(wr_l.q) # busy if set
 141         m.d.comb += xx_pend_o.eq(dest_d.o)
 142
 143         # src1/src2 decoder: read-pending out
 144         m.d.comb += src1_d.i.eq(self.src1_i)
 145         m.d.comb += src1_d.n.eq(rd_l.qn) # decode is inverted
 146         m.d.comb += src2_d.i.eq(self.src2_i)
 147         m.d.comb += src2_d.n.eq(rd_l.qn) # decode is inverted
 148         m.d.comb += self.src1_pend_o.eq(src1_d.o)
 149         m.d.comb += self.src2_pend_o.eq(src2_d.o)
 150         m.d.comb += self.rd_pend_o.eq(src1_d.o | src2_d.o)
 151
 152         # readable output signal
 153         g_rd = Signal(self.reg_width, reset_less=True)
 154         m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
 155         m.d.comb += self.readable_o.eq(g_rd.bool())
 156
 157         # writable output signal
 158         g_wr_v = Signal(self.reg_width, reset_less=True)
 159         g_wr = Signal(reset_less=True)
 160         wo = Signal(reset_less=True)
 161         m.d.comb += g_wr_v.eq(g_pend_i & xx_pend_o)
 162         m.d.comb += g_wr.eq(~g_wr_v.bool())
 163         m.d.comb += wo.eq(g_wr & rd_l.qn & self.req_rel_i & shadown)
 164         m.d.comb += writable_o.eq(wo)
 165
 166         return m
 167
 168     def __iter__(self):
 169         yield self.dest_i
 170         yield self.src1_i
 171         yield self.src2_i
 172         yield self.issue_i
 173         yield self.go_wr_i
 174         yield self.go_rd_i
 175         yield self.req_rel_i
 176         yield from self.g_xx_pend_i
 177         yield self.g_wr_pend_i
 178         yield self.readable_o
 179         yield from self.writable_o
 180         yield self.rd_pend_o
 181         yield from self.xx_pend_o
 182
 183     def ports(self):
 184         return list(self)
 185
 186 #############                                     ###############
 187 # ---                                                       --- #
 188 # --- renamed / redirected from base class                  --- #
 189 # ---                                                       --- #
 190 # --- below are convenience classes which match the names   --- #
 191 # --- of the various mitch alsup book chapter gate diagrams --- #
 192 # ---                                                       --- #
 193 #############                                     ###############
 194
 195
 196 class IntFnUnit(FnUnit):
 197     def __init__(self, wid, shadow_wid=0):
 198         FnUnit.__init__(self, wid, shadow_wid)
 199         self.int_rd_pend_o = self.rd_pend_o
 200         self.int_wr_pend_o = self.xx_pend_o[0]
 201         self.g_int_wr_pend_i = self.g_wr_pend_i
 202         self.g_int_rd_pend_i = self.g_xx_pend_i[0]
 203         self.int_readable_o = self.readable_o
 204         self.int_writable_o = self.writable_o[0]
 205
 206         self.int_rd_pend_o.name = "int_rd_pend_o"
 207         self.int_wr_pend_o.name = "int_wr_pend_o"
 208         self.g_int_rd_pend_i.name = "g_int_rd_pend_i"
 209         self.g_int_wr_pend_i.name = "g_int_wr_pend_i"
 210         self.int_readable_o.name = "int_readable_o"
 211         self.int_writable_o.name = "int_writable_o"
 212
 213
 214 class FPFnUnit(FnUnit):
 215     def __init__(self, wid, shadow_wid=0):
 216         FnUnit.__init__(self, wid, shadow_wid)
 217         self.fp_rd_pend_o = self.rd_pend_o
 218         self.fp_wr_pend_o = self.xx_pend_o[0]
 219         self.g_fp_wr_pend_i = self.g_wr_pend_i
 220         self.g_fp_rd_pend_i = self.g_xx_pend_i[0]
 221         self.fp_writable_o = self.writable_o[0]
 222         self.fp_readable_o = self.readable_o
 223
 224         self.fp_rd_pend_o.name = "fp_rd_pend_o"
 225         self.fp_wr_pend_o.name = "fp_wr_pend_o"
 226         self.g_fp_rd_pend_i.name = "g_fp_rd_pend_i"
 227         self.g_fp_wr_pend_i.name = "g_fp_wr_pend_i"
 228         self.fp_writable_o.name = "fp_writable_o"
 229         self.fp_readable_o.name = "fp_readable_o"
 230
 231
 232 class LDFnUnit(FnUnit):
 233     """ number of dest selectors: 2. assumes len(int_regfile) == len(fp_regfile)
 234         * when rfile_sel_i == 0, int_wr_pend_o is set
 235         * when rfile_sel_i == 1, fp_wr_pend_o is set
 236     """
 237     def __init__(self, wid, shadow_wid=0):
 238         FnUnit.__init__(self, wid, shadow_wid, n_dests=2)
 239         self.int_rd_pend_o = self.rd_pend_o
 240         self.int_wr_pend_o = self.xx_pend_o[0]
 241         self.fp_wr_pend_o = self.xx_pend_o[1]
 242         self.g_int_wr_pend_i = self.g_wr_pend_i
 243         self.g_int_rd_pend_i = self.g_xx_pend_i[0]
 244         self.g_fp_rd_pend_i = self.g_xx_pend_i[1]
 245         self.int_readable_o = self.readable_o
 246         self.int_writable_o = self.writable_o[0]
 247         self.fp_writable_o = self.writable_o[1]
 248
 249         self.int_rd_pend_o.name = "int_rd_pend_o"
 250         self.int_wr_pend_o.name = "int_wr_pend_o"
 251         self.fp_wr_pend_o.name = "fp_wr_pend_o"
 252         self.g_int_wr_pend_i.name = "g_int_wr_pend_i"
 253         self.g_int_rd_pend_i.name = "g_int_rd_pend_i"
 254         self.g_fp_rd_pend_i.name = "g_fp_rd_pend_i"
 255         self.int_readable_o.name = "int_readable_o"
 256         self.int_writable_o.name = "int_writable_o"
 257         self.fp_writable_o.name = "fp_writable_o"
 258
 259
 260 class STFnUnit(FnUnit):
 261     """ number of dest selectors: 2. assumes len(int_regfile) == len(fp_regfile)
 262         * wr_pend=False indicates to observe global fp write pending
 263         * when rfile_sel_i == 0, int_wr_pend_o is set
 264         * when rfile_sel_i == 1, fp_wr_pend_o is set
 265         *
 266     """
 267     def __init__(self, wid, shadow_wid=0):
 268         FnUnit.__init__(self, wid, shadow_wid, n_dests=2, wr_pend=True)
 269         self.int_rd_pend_o = self.rd_pend_o     # 1st int read-pending vector
 270         self.int2_rd_pend_o = self.xx_pend_o[0] # 2nd int read-pending vector
 271         self.fp_rd_pend_o = self.xx_pend_o[1]   # 1x FP read-pending vector
 272         # yes overwrite FnUnit base class g_wr_pend_i vector
 273         self.g_int_wr_pend_i = self.g_wr_pend_i = self.g_xx_pend_i[0]
 274         self.g_fp_wr_pend_i = self.g_xx_pend_i[1]
 275         self.int_readable_o = self.readable_o
 276         self.int_writable_o = self.writable_o[0]
 277         self.fp_writable_o = self.writable_o[1]
 278
 279         self.int_rd_pend_o.name = "int_rd_pend_o"
 280         self.int2_rd_pend_o.name = "int2_rd_pend_o"
 281         self.fp_rd_pend_o.name = "fp_rd_pend_o"
 282         self.g_int_wr_pend_i.name = "g_int_wr_pend_i"
 283         self.g_fp_wr_pend_i.name = "g_fp_wr_pend_i"
 284         self.int_readable_o.name = "int_readable_o"
 285         self.int_writable_o.name = "int_writable_o"
 286         self.fp_writable_o.name = "fp_writable_o"
 287
 288
 289
 290 def int_fn_unit_sim(dut):
 291     yield dut.dest_i.eq(1)
 292     yield dut.issue_i.eq(1)
 293     yield
 294     yield dut.issue_i.eq(0)
 295     yield
 296     yield dut.src1_i.eq(1)
 297     yield dut.issue_i.eq(1)
 298     yield
 299     yield
 300     yield
 301     yield dut.issue_i.eq(0)
 302     yield
 303     yield dut.go_rd_i.eq(1)
 304     yield
 305     yield dut.go_rd_i.eq(0)
 306     yield
 307     yield dut.go_wr_i.eq(1)
 308     yield
 309     yield dut.go_wr_i.eq(0)
 310     yield
 311
 312 def test_int_fn_unit():
 313     dut = FnUnit(32, 2, 2)
 314     vl = rtlil.convert(dut, ports=dut.ports())
 315     with open("test_fn_unit.il", "w") as f:
 316         f.write(vl)
 317
 318     dut = LDFnUnit(32, 2)
 319     vl = rtlil.convert(dut, ports=dut.ports())
 320     with open("test_ld_fn_unit.il", "w") as f:
 321         f.write(vl)
 322
 323     dut = STFnUnit(32, 0)
 324     vl = rtlil.convert(dut, ports=dut.ports())
 325     with open("test_st_fn_unit.il", "w") as f:
 326         f.write(vl)
 327
 328     run_simulation(dut, int_fn_unit_sim(dut), vcd_name='test_fn_unit.vcd')
 329
 330 if __name__ == '__main__':
 331     test_int_fn_unit()