src/scoreboard/fu_dep_cell.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4 from nmutil.latch import SRLatch
   5
   6
   7 class DepCell(Elaboratable):
   8     """ FU Dependency Cell
   9     """
  10     def __init__(self):
  11         # inputs
  12         self.pend_i = Signal(reset_less=True)    # pending bit in (left)
  13         self.issue_i = Signal(reset_less=True)   # Issue in (top)
  14         self.go_i = Signal(reset_less=True)      # Go read/write in (left)
  15
  16         # wait
  17         self.wait_o = Signal(reset_less=True)  # wait out (right)
  18
  19     def elaborate(self, platform):
  20         m = Module()
  21         m.submodules.l = l = SRLatch(sync=False) # async latch
  22
  23         # reset on go HI, set on dest and issue
  24         m.d.comb += l.s.eq(self.issue_i & self.pend_i)
  25         m.d.comb += l.r.eq(self.go_i)
  26
  27         # wait out
  28         m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i)
  29
  30         return m
  31
  32     def __iter__(self):
  33         yield self.pend_i
  34         yield self.issue_i
  35         yield self.go_i
  36         yield self.wait_o
  37
  38     def ports(self):
  39         return list(self)
  40
  41
  42 class FUDependenceCell(Elaboratable):
  43     """ implements 11.4.7 mitch alsup dependence cell, p27
  44     """
  45     def __init__(self):
  46         # inputs
  47         self.rd_pend_i = Signal(reset_less=True)     # read pending in (left)
  48         self.wr_pend_i = Signal(reset_less=True)     # write pending in (left)
  49         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  50
  51         self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
  52         self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
  53
  54         # outputs (latched rd/wr wait)
  55         self.rd_wait_o = Signal(reset_less=True)   # read waiting out (right)
  56         self.wr_wait_o = Signal(reset_less=True)   # write waiting out (right)
  57
  58     def elaborate(self, platform):
  59         m = Module()
  60         m.submodules.rd_c = rd_c = DepCell()
  61         m.submodules.wr_c = wr_c = DepCell()
  62
  63         # connect issue
  64         for c in [rd_c, wr_c]:
  65             m.d.comb += c.issue_i.eq(self.issue_i)
  66
  67         # connect go_rd / go_wr
  68         m.d.comb += wr_c.go_i.eq(self.go_wr_i)
  69         m.d.comb += rd_c.go_i.eq(self.go_rd_i)
  70
  71         # connect pend_i
  72         m.d.comb += wr_c.pend_i.eq(self.wr_pend_i)
  73         m.d.comb += rd_c.pend_i.eq(self.rd_pend_i)
  74
  75         # connect output
  76         m.d.comb += self.wr_wait_o.eq(wr_c.wait_o)
  77         m.d.comb += self.rd_wait_o.eq(rd_c.wait_o)
  78
  79         return m
  80
  81     def __iter__(self):
  82         yield self.rd_pend_i
  83         yield self.wr_pend_i
  84         yield self.issue_i
  85         yield self.go_wr_i
  86         yield self.go_rd_i
  87         yield self.rd_wait_o
  88         yield self.wr_wait_o
  89
  90     def ports(self):
  91         return list(self)
  92
  93
  94 def dcell_sim(dut):
  95     yield dut.dest_i.eq(1)
  96     yield dut.issue_i.eq(1)
  97     yield
  98     yield dut.issue_i.eq(0)
  99     yield
 100     yield dut.src1_i.eq(1)
 101     yield dut.issue_i.eq(1)
 102     yield
 103     yield dut.issue_i.eq(0)
 104     yield
 105     yield dut.go_rd_i.eq(1)
 106     yield
 107     yield dut.go_rd_i.eq(0)
 108     yield
 109     yield dut.go_wr_i.eq(1)
 110     yield
 111     yield dut.go_wr_i.eq(0)
 112     yield
 113
 114 def test_dcell():
 115     dut = FUDependenceCell()
 116     vl = rtlil.convert(dut, ports=dut.ports())
 117     with open("test_fu_dcell.il", "w") as f:
 118         f.write(vl)
 119
 120     run_simulation(dut, dcell_sim(dut), vcd_name='test_fu_dcell.vcd')
 121
 122 if __name__ == '__main__':
 123     test_dcell()