1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
4 from nmutil
.latch
import SRLatch
6 class DepCell(Elaboratable
):
11 self
.pend_i
= Signal(reset_less
=True) # pending bit in (left)
12 self
.issue_i
= Signal(reset_less
=True) # Issue in (top)
13 self
.go_i
= Signal(reset_less
=True) # Go read/write in (left)
16 self
.wait_o
= Signal(reset_less
=True) # wait out (right)
18 def elaborate(self
, platform
):
20 m
.submodules
.l
= l
= SRLatch(sync
=False) # async latch
22 # record current version of q in a sync'd register
23 cq
= Signal() # resets to 0
24 m
.d
.sync
+= cq
.eq(l
.q
)
26 # reset on go HI, set on dest and issue
27 m
.d
.comb
+= l
.s
.eq(self
.issue_i
& self
.pend_i
)
28 m
.d
.comb
+= l
.r
.eq(self
.go_i
)
31 m
.d
.comb
+= self
.wait_o
.eq((cq | l
.q
) & ~self
.issue_i
)
45 class FUDependenceCell(Elaboratable
):
46 """ implements 11.4.7 mitch alsup dependence cell, p27
50 self
.rd_pend_i
= Signal(reset_less
=True) # read pending in (left)
51 self
.wr_pend_i
= Signal(reset_less
=True) # write pending in (left)
52 self
.issue_i
= Signal(reset_less
=True) # Issue in (top)
54 self
.go_wr_i
= Signal(reset_less
=True) # Go Write in (left)
55 self
.go_rd_i
= Signal(reset_less
=True) # Go Read in (left)
57 # outputs (latched rd/wr wait)
58 self
.rd_wait_o
= Signal(reset_less
=True) # read waiting out (right)
59 self
.wr_wait_o
= Signal(reset_less
=True) # write waiting out (right)
61 def elaborate(self
, platform
):
63 m
.submodules
.rd_c
= rd_c
= DepCell()
64 m
.submodules
.wr_c
= wr_c
= DepCell()
67 for c
in [rd_c
, wr_c
]:
68 m
.d
.comb
+= c
.issue_i
.eq(self
.issue_i
)
70 # connect go_rd / go_wr
71 m
.d
.comb
+= wr_c
.go_i
.eq(self
.go_wr_i
)
72 m
.d
.comb
+= rd_c
.go_i
.eq(self
.go_rd_i
)
75 m
.d
.comb
+= wr_c
.go_i
.eq(self
.wr_pend_i
)
76 m
.d
.comb
+= rd_c
.go_i
.eq(self
.rd_pend_i
)
79 m
.d
.comb
+= self
.wr_wait_o
.eq(wr_c
.wait_o
)
80 m
.d
.comb
+= self
.rd_wait_o
.eq(rd_c
.wait_o
)
98 yield dut
.dest_i
.eq(1)
99 yield dut
.issue_i
.eq(1)
101 yield dut
.issue_i
.eq(0)
103 yield dut
.src1_i
.eq(1)
104 yield dut
.issue_i
.eq(1)
106 yield dut
.issue_i
.eq(0)
108 yield dut
.go_rd_i
.eq(1)
110 yield dut
.go_rd_i
.eq(0)
112 yield dut
.go_wr_i
.eq(1)
114 yield dut
.go_wr_i
.eq(0)
118 dut
= FUDependenceCell()
119 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
120 with
open("test_fu_dcell.il", "w") as f
:
123 run_simulation(dut
, dcell_sim(dut
), vcd_name
='test_fu_dcell.vcd')
125 if __name__
== '__main__':