1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
, Array
, Cat
, Const
5 #from nmutil.latch import SRLatch
6 from .fu_dep_cell
import FUDependenceCell
7 from .fu_picker_vec
import FU_Pick_Vec
11 6600 Function Unit Dependency Table Matrix inputs / outputs
12 -----------------------------------------------------------
16 class FUFUDepMatrix(Elaboratable
):
17 """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
19 def __init__(self
, n_fu_row
, n_fu_col
):
20 self
.n_fu_row
= n_fu_row
# Y (FU row#) ^v
21 self
.n_fu_col
= n_fu_col
# X (FU col #) <>
22 self
.rd_pend_i
= Signal(n_fu_row
, reset_less
=True) # Rd pending (left)
23 self
.wr_pend_i
= Signal(n_fu_row
, reset_less
=True) # Wr pending (left)
24 self
.issue_i
= Signal(n_fu_col
, reset_less
=True) # Issue in (top)
26 self
.go_wr_i
= Signal(n_fu_row
, reset_less
=True) # Go Write in (left)
27 self
.go_rd_i
= Signal(n_fu_row
, reset_less
=True) # Go Read in (left)
29 # for Function Unit Readable/Writable (horizontal)
30 self
.readable_o
= Signal(n_fu_col
, reset_less
=True) # readable (bot)
31 self
.writable_o
= Signal(n_fu_col
, reset_less
=True) # writable (bot)
33 def elaborate(self
, platform
):
37 # matrix of dependency cells
39 dm
= Array(Array(FUDependenceCell() for r
in range(self
.n_fu_row
)) \
40 for f
in range(self
.n_fu_col
))
41 for x
in range(self
.n_fu_col
):
42 for y
in range(self
.n_fu_row
):
43 setattr(m
.submodules
, "dm_fx%d_fy%d" % (x
, y
), dm
[x
][y
])
46 # array of Function Unit Readable/Writable: row-length, horizontal
48 fur
= Array(FU_Pick_Vec(self
.n_fu_row
) for r
in range(self
.n_fu_col
))
49 for x
in range(self
.n_fu_col
):
50 setattr(m
.submodules
, "fur_x%d" % (x
), fur
[x
])
53 # connect FU Readable/Writable vector
57 for x
in range(self
.n_fu_col
):
59 # accumulate Readable/Writable Vector outputs
60 readable
.append(fu
.readable_o
)
61 writable
.append(fu
.writable_o
)
63 # ... and output them from this module (horizontal, width=REGs)
64 m
.d
.comb
+= self
.readable_o
.eq(Cat(*readable
))
65 m
.d
.comb
+= self
.writable_o
.eq(Cat(*writable
))
70 for y
in range(self
.n_fu_row
):
74 for x
in range(self
.n_fu_col
):
76 # accumulate cell outputs rd/wr-pending
77 rd_wait_o
.append(dc
.rd_wait_o
)
78 wr_wait_o
.append(dc
.wr_wait_o
)
79 # connect cell reg-select outputs to Reg Vector In
80 m
.d
.comb
+= [fu
.rd_pend_i
.eq(Cat(*rd_wait_o
)),
81 fu
.wr_pend_i
.eq(Cat(*wr_wait_o
)),
84 # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
86 for x
in range(self
.n_fu_col
):
88 for y
in range(self
.n_fu_row
):
90 # accumulate cell inputs issue
91 issue_i
.append(dc
.issue_i
)
92 # wire up inputs from module to row cell inputs (Cat is gooood)
93 m
.d
.comb
+= Cat(*issue_i
).eq(self
.issue_i
)
96 # connect Matrix go_rd_i/go_wr_i to module readable/writable
98 for y
in range(self
.n_fu_row
):
101 for x
in range(self
.n_fu_col
):
103 # accumulate cell go_rd/go_wr
104 go_rd_i
.append(dc
.go_rd_i
)
105 go_wr_i
.append(dc
.go_wr_i
)
106 # wire up inputs from module to row cell inputs (Cat is gooood)
107 m
.d
.comb
+= [Cat(*go_rd_i
).eq(self
.go_rd_i
),
108 Cat(*go_wr_i
).eq(self
.go_wr_i
),
112 # connect Matrix pending
114 for y
in range(self
.n_fu_row
):
117 for x
in range(self
.n_fu_col
):
118 if x
== y
: # ignore hazards on the diagonal: self-against-self
119 dummyrd
= Signal(reset_less
=True)
120 dummywr
= Signal(reset_less
=True)
121 rd_pend_i
.append(dummyrd
)
122 wr_pend_i
.append(dummywr
)
125 # accumulate cell rd_pend/wr_pend/go_rd/go_wr
126 rd_pend_i
.append(dc
.rd_pend_i
)
127 wr_pend_i
.append(dc
.wr_pend_i
)
128 # wire up inputs from module to row cell inputs (Cat is gooood)
129 m
.d
.comb
+= [Cat(*rd_pend_i
).eq(self
.rd_pend_i
),
130 Cat(*wr_pend_i
).eq(self
.wr_pend_i
),
141 yield self
.readable_o
142 yield self
.writable_o
147 def d_matrix_sim(dut
):
150 yield dut
.dest_i
.eq(1)
151 yield dut
.issue_i
.eq(1)
153 yield dut
.issue_i
.eq(0)
155 yield dut
.src1_i
.eq(1)
156 yield dut
.issue_i
.eq(1)
158 yield dut
.issue_i
.eq(0)
160 yield dut
.go_rd_i
.eq(1)
162 yield dut
.go_rd_i
.eq(0)
164 yield dut
.go_wr_i
.eq(1)
166 yield dut
.go_wr_i
.eq(0)
169 def test_fu_fu_matrix():
170 dut
= FUFUDepMatrix(n_fu_row
=3, n_fu_col
=4)
171 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
172 with
open("test_fu_fu_matrix.il", "w") as f
:
175 run_simulation(dut
, d_matrix_sim(dut
), vcd_name
='test_fu_fu_matrix.vcd')
177 if __name__
== '__main__':