1 from nmigen
import Elaboratable
, Module
, Signal
, Cat
4 class FU_Pick_Vec(Elaboratable
):
5 """ these are allocated per-FU (horizontally),
6 and are of length fu_row_n
8 def __init__(self
, fu_row_n
):
9 self
.fu_row_n
= fu_row_n
10 self
.rd_pend_i
= Signal(fu_row_n
, reset_less
=True)
11 self
.wr_pend_i
= Signal(fu_row_n
, reset_less
=True)
13 self
.readable_o
= Signal(reset_less
=True)
14 self
.writable_o
= Signal(reset_less
=True)
16 def elaborate(self
, platform
):
18 m
.d
.comb
+= self
.readable_o
.eq(~self
.rd_pend_i
.bool())
19 m
.d
.comb
+= self
.writable_o
.eq(~self
.wr_pend_i
.bool())