1 from nmigen
import Elaboratable
, Module
, Signal
, Cat
4 class FU_RW_Pend(Elaboratable
):
5 """ these are allocated per-FU (horizontally),
6 and are of length reg_count
8 def __init__(self
, reg_count
):
9 self
.reg_count
= reg_count
10 self
.dest_fwd_i
= Signal(reg_count
, reset_less
=True)
11 self
.src1_fwd_i
= Signal(reg_count
, reset_less
=True)
12 self
.src2_fwd_i
= Signal(reg_count
, reset_less
=True)
14 self
.reg_wr_pend_o
= Signal(reset_less
=True)
15 self
.reg_rd_pend_o
= Signal(reset_less
=True)
17 def elaborate(self
, platform
):
19 srces
= Cat(self
.src1_fwd_i
, self
.src2_fwd_i
)
20 m
.d
.comb
+= self
.reg_wr_pend_o
.eq(self
.dest_fwd_i
.bool())
21 m
.d
.comb
+= self
.reg_rd_pend_o
.eq(srces
.bool())