1 from nmigen
import Elaboratable
, Module
, Signal
4 class FUReadWritePending(Elaboratable
):
5 def __init__(self
, reg_count
):
6 self
.reg_count
= reg_count
7 self
.dest_fwd_i
= Signal(fu_count
, reset_less
=True)
8 self
.src1_fwd_i
= Signal(fu_count
, reset_less
=True)
9 self
.src2_fwd_i
= Signal(fu_count
, reset_less
=True)
11 self
.wr_pend_o
= Signal(reset_less
=True)
12 self
.rd_pend_o
= Signal(reset_less
=True)
14 def elaboratable(self
, platform
):
16 srces
= Cat(self
.src1_fwd_i
, self
.src2_fwd_i
)
17 m
.d
.comb
+= self
.wr_pend_o
.eq(self
.dest_fwd_i
.bool())
18 m
.d
.comb
+= self
.rd_pend_o
.eq(srces
.bool()