1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Elaboratable
6 class GlobalPending(Elaboratable
):
7 """ implements Global Pending Vector, basically ORs all incoming Function
8 Unit vectors together. Can be used for creating Read or Write Global
9 Pending. Can be used for INT or FP Global Pending.
12 * :dep: register file depth
13 * :fu_vecs: a python list of function unit "pending" vectors, each
14 vector being a Signal of width equal to the reg file.
18 * the regfile may be Int or FP, this code doesn't care which.
19 obviously do not try to put in a mixture of regfiles into fu_vecs.
20 * this code also doesn't care if it's used for Read Pending or Write
21 pending, it can be used for both: again, obviously, do not try to
22 put in a mixture of read *and* write pending vectors in.
23 * if some Function Units happen not to be uniform (don't operate
24 on a particular register (extremely unusual), they must set a Const
25 zero bit in the vector.
27 def __init__(self
, dep
, fu_vecs
, sync
=False):
30 self
.fu_vecs
= fu_vecs
33 assert len(v
) == dep
, "FU Vector must be same width as regfile"
35 self
.g_pend_o
= Signal(dep
, reset_less
=True) # global pending vector
37 def elaborate(self
, platform
):
41 for i
in range(self
.reg_dep
): # per-register
43 for v
in self
.fu_vecs
:
44 vec_bit_l
.append(v
[i
]) # fu bit for same register
45 pend_l
.append(Cat(*vec_bit_l
).bool()) # OR all bits for same reg
47 m
.d
.sync
+= self
.g_pend_o
.eq(Cat(*pend_l
)) # merge all OR'd bits
49 m
.d
.comb
+= self
.g_pend_o
.eq(Cat(*pend_l
)) # merge all OR'd bits
54 yield from self
.fu_vecs
62 yield dut
.dest_i
.eq(1)
63 yield dut
.issue_i
.eq(1)
65 yield dut
.issue_i
.eq(0)
67 yield dut
.src1_i
.eq(1)
68 yield dut
.issue_i
.eq(1)
72 yield dut
.issue_i
.eq(0)
74 yield dut
.go_rd_i
.eq(1)
76 yield dut
.go_rd_i
.eq(0)
78 yield dut
.go_wr_i
.eq(1)
80 yield dut
.go_wr_i
.eq(0)
86 vecs
.append(Signal(32, name
="fu%d" % i
))
87 dut
= GlobalPending(32, vecs
)
88 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
89 with
open("test_global_pending.il", "w") as f
:
92 run_simulation(dut
, g_vec_sim(dut
), vcd_name
='test_global_pending.vcd')
94 if __name__
== '__main__':