1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Array
, Const
, Record
, Elaboratable
4 from nmigen
.lib
.coding
import Decoder
6 from .shadow_fn
import ShadowFn
9 class IssueUnit(Elaboratable
):
10 """ implements 11.4.14 issue unit, p50
14 * :wid: register file width
15 * :n_insns: number of instructions in this issue unit.
17 def __init__(self
, wid
, n_insns
):
19 self
.n_insns
= n_insns
22 self
.store_i
= Signal(reset_less
=True) # instruction is a store
23 self
.dest_i
= Signal(max=wid
, reset_less
=True) # Dest R# in
24 self
.src1_i
= Signal(max=wid
, reset_less
=True) # oper1 R# in
25 self
.src2_i
= Signal(max=wid
, reset_less
=True) # oper2 R# in
27 self
.g_wr_pend_i
= Signal(wid
, reset_less
=True) # write pending vector
29 self
.insn_i
= Array(Signal(reset_less
=True, name
="insn_i") \
30 for i
in range(n_insns
))
31 self
.busy_i
= Array(Signal(reset_less
=True, name
="busy_i") \
32 for i
in range(n_insns
))
35 self
.fn_issue_o
= Array(Signal(reset_less
=True, name
="fn_issue_o") \
36 for i
in range(n_insns
))
37 self
.g_issue_o
= Signal(reset_less
=True)
39 def elaborate(self
, platform
):
41 m
.submodules
.dest_d
= dest_d
= Decoder(self
.reg_width
)
47 waw_stall
= Signal(reset_less
=True)
48 fu_stall
= Signal(reset_less
=True)
49 pend
= Signal(self
.reg_width
, reset_less
=True)
51 # dest decoder: write-pending
52 m
.d
.comb
+= dest_d
.i
.eq(self
.dest_i
)
53 m
.d
.comb
+= dest_d
.n
.eq(~self
.store_i
) # decode is inverted
54 m
.d
.comb
+= pend
.eq(dest_d
.o
& self
.g_wr_pend_i
)
55 m
.d
.comb
+= waw_stall
.eq(pend
.bool())
58 for i
in range(self
.n_insns
):
59 ib_l
.append(self
.insn_i
[i
] & self
.busy_i
[i
])
60 m
.d
.comb
+= fu_stall
.eq(Cat(*ib_l
).bool())
61 m
.d
.comb
+= self
.g_issue_o
.eq(~
(waw_stall | fu_stall
))
62 for i
in range(self
.n_insns
):
63 m
.d
.comb
+= self
.fn_issue_o
[i
].eq(self
.g_issue_o
& self
.insn_i
[i
])
72 yield self
.g_wr_pend_i
73 yield from self
.insn_i
74 yield from self
.busy_i
75 yield from self
.fn_issue_o
82 class IntFPIssueUnit(Elaboratable
):
83 def __init__(self
, wid
, n_int_insns
, n_fp_insns
):
84 self
.i
= IssueUnit(wid
, n_int_insns
)
85 self
.f
= IssueUnit(wid
, n_fp_insns
)
86 self
.issue_o
= Signal(reset_less
=True)
89 self
.int_write_pending_i
= self
.i
.g_wr_pend_i
90 self
.fp_write_pending_i
= self
.f
.g_wr_pend_i
91 self
.int_write_pending_i
.name
= 'int_write_pending_i'
92 self
.fp_write_pending_i
.name
= 'fp_write_pending_i'
94 def elaborate(self
, platform
):
96 m
.submodules
.intissue
= self
.i
97 m
.submodules
.fpissue
= self
.f
99 m
.d
.comb
+= self
.issue_o
.eq(self
.i
.g_issue_o | self
.f
.g_issue_o
)
109 def issue_unit_sim(dut
):
110 yield dut
.dest_i
.eq(1)
111 yield dut
.issue_i
.eq(1)
113 yield dut
.issue_i
.eq(0)
115 yield dut
.src1_i
.eq(1)
116 yield dut
.issue_i
.eq(1)
120 yield dut
.issue_i
.eq(0)
122 yield dut
.go_rd_i
.eq(1)
124 yield dut
.go_rd_i
.eq(0)
126 yield dut
.go_wr_i
.eq(1)
128 yield dut
.go_wr_i
.eq(0)
131 def test_issue_unit():
132 dut
= IssueUnit(32, 3)
133 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
134 with
open("test_issue_unit.il", "w") as f
:
137 dut
= IntFPIssueUnit(32, 3, 3)
138 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
139 with
open("test_intfp_issue_unit.il", "w") as f
:
142 run_simulation(dut
, issue_unit_sim(dut
), vcd_name
='test_issue_unit.vcd')
144 if __name__
== '__main__':