1 from nmigen
import Elaboratable
, Module
, Signal
4 class Reg_Rsv(Elaboratable
):
5 """ these are allocated per-Register (vertically),
6 and are each of length fu_count
8 def __init__(self
, fu_count
):
9 self
.fu_count
= fu_count
10 self
.dest_rsel_i
= Signal(fu_count
, reset_less
=True)
11 self
.src1_rsel_i
= Signal(fu_count
, reset_less
=True)
12 self
.src2_rsel_i
= Signal(fu_count
, reset_less
=True)
13 self
.dest_rsel_o
= Signal(reset_less
=True)
14 self
.src1_rsel_o
= Signal(reset_less
=True)
15 self
.src2_rsel_o
= Signal(reset_less
=True)
17 def elaborate(self
, platform
):
19 m
.d
.comb
+= self
.dest_rsel_o
.eq(self
.dest_rsel_i
.bool())
20 m
.d
.comb
+= self
.src1_rsel_o
.eq(self
.src1_rsel_i
.bool())
21 m
.d
.comb
+= self
.src2_rsel_o
.eq(self
.src2_rsel_i
.bool())