1 """ testing of InstructionQ
4 from copy
import deepcopy
5 from random
import randint
6 from nmigen
.compat
.sim
import run_simulation
7 from nmigen
.cli
import verilog
, rtlil
9 from scoreboard
.instruction_q
import InstructionQ
10 from nmutil
.nmoperator
import eq
14 def __init__(self
, dut
, iq
, n_in
, n_out
):
23 while i
< len(self
.iq
):
24 sendlen
= randint(1, self
.n_in
)
26 sendlen
= min(len(self
.iq
) - i
, sendlen
)
27 print (len(self
.iq
)-i
, sendlen
)
28 for idx
in range(sendlen
):
29 instr
= self
.iq
[i
+idx
]
30 yield from eq(self
.dut
.data_i
[idx
], instr
)
31 yield self
.dut
.p_add_i
.eq(sendlen
)
32 o_p_ready
= yield self
.dut
.p_ready_o
35 o_p_ready
= yield self
.dut
.p_ready_o
38 yield self
.dut
.p_add_i
.eq(0)
40 print ("send", len(self
.iq
), i
, sendlen
)
42 # wait random period of time before queueing another value
43 for j
in range(randint(0, 3)):
48 yield self
.dut
.p_add_i
.eq(0)
53 ## wait random period of time before queueing another value
54 #for i in range(randint(0, 3)):
57 #send_range = randint(0, 3)
61 # send = randint(0, send_range) != 0
68 while i
< len(self
.iq
):
69 rcvlen
= randint(1, self
.n_out
)
70 #print ("outreq", rcvlen)
71 yield self
.dut
.n_sub_i
.eq(rcvlen
)
72 n_sub_o
= yield self
.dut
.n_sub_o
77 print ("recv", n_sub_o
)
83 def mk_insns(n_insns
, wid
, opwid
):
85 for i
in range(n_insns
):
86 op1
= randint(0, (1<<wid
)-1)
87 op2
= randint(0, (1<<wid
)-1)
88 dst
= randint(0, (1<<wid
)-1)
89 oper
= randint(0, (1<<opwid
)-1)
90 res
.append({'oper_i': oper
, 'dest_i': dst
, 'src1_i': op1
, 'src2_i': op2
})
100 dut
= InstructionQ(wid
, opwid
, qlen
, n_in
, n_out
)
101 insns
= mk_insns(10, wid
, opwid
)
103 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
104 with
open("test_iq.il", "w") as f
:
107 test
= IQSim(dut
, insns
, n_in
, n_out
)
109 run_simulation(dut
, [test
.rcv(), test
.send()
111 vcd_name
="test_iq.vcd")
113 if __name__
== '__main__':