1 from nmigen
.compat
.sim
import run_simulation
3 from soc
.TLB
.ariane
.tlb
import TLB
7 yield dut
.lu_vaddr_i
.eq(addr
)
8 yield dut
.update_i
.vpn
.eq(addr
>> 12)
12 yield dut
.lu_access_i
.eq(1)
13 yield dut
.lu_asid_i
.eq(1)
14 yield dut
.update_i
.valid
.eq(1)
15 yield dut
.update_i
.is_1G
.eq(0)
16 yield dut
.update_i
.is_2M
.eq(0)
17 yield dut
.update_i
.asid
.eq(1)
18 yield dut
.update_i
.content
.ppn
.eq(0)
19 yield dut
.update_i
.content
.rsw
.eq(0)
20 yield dut
.update_i
.content
.r
.eq(1)
25 yield from set_vaddr(addr
)
29 yield from set_vaddr(addr
)
33 yield from set_vaddr(addr
)
37 yield from set_vaddr(addr
)
40 yield from set_vaddr(addr
)
44 yield from set_vaddr(addr
)
48 yield from set_vaddr(addr
)
51 yield dut
.update_i
.is_1G
.eq(1)
53 yield from set_vaddr(addr
)
56 yield dut
.update_i
.is_1G
.eq(1)
58 yield from set_vaddr(addr
)
64 if __name__
== "__main__":
66 run_simulation(dut
, tbench(dut
), vcd_name
="test_tlb.vcd")
67 print("TLB Unit Test Success")