src/soc/alu/input_stage.py

   1 from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
   2                     unsigned)
   3 from nmutil.pipemodbase import PipeModBase
   4 from soc.alu.pipe_data import ALUInitialData
   5
   6
   7 class ALUInputStage(PipeModBase):
   8     def __init__(self, pspec):
   9         super().__init__(pspec, "input")
  10
  11     def ispec(self):
  12         return ALUInitialData(self.pspec)
  13
  14     def ospec(self):
  15         return ALUInitialData(self.pspec)
  16
  17     def elaborate(self, platform):
  18         m = Module()
  19         comb = m.d.comb
  20
  21         comb += self.o.op.eq(self.i.op)
  22
  23         a = Signal.like(self.i.a)
  24
  25         with m.If(self.i.op.invert_a):
  26             comb += a.eq(~self.i.a)
  27         with m.Else():
  28             comb += a.eq(self.i.a)
  29
  30         comb += self.o.a.eq(a)
  31
  32         comb += self.o.b.eq(self.i.b)
  33
  34         return m